Simulate Translate Test

Using VCAP's Clock Identifier Feature

Cyclization is the process of collapsing Event-based vector formats produced in design into Cycle-based vector formats used on ATE hardware. It is possibly the most challenging task of the translation operation. Choosing the CYCLE length is a fundamental part of cyclization. It specifies the amount of time per tester cycle and drives the sampling and timing generation functions of the translation. Because the CYCLE length is most often a value related to the basic clock of the device, it makes sense to know the clock behaviours on device input signals. This application note describes how to use the VCAP® Clock Identifier feature to get detailed information on the clock behaviour of device input signals for the purpose of determining optimal CYCLE length.

Translation Process Overview

The actual conversion of VCD/EVCD files with print on change formats (POC) files to ATE test programs files is done by VTRAN® . VTRAN® gathers state data from the Original Vector File, cyclizes it, applies user-specified processing, maps state characters between the two formats, applies target timing, and generates a Target Vector File. VTRAN® execution is controlled by a command file generated by the user. If desired, the user has the option to use both the clock identifier and timing analysis features of VCAP® to support the construction of the VTRAN® command file. VCAP® execution is also controlled by a user command file. Finally, DFTView® can be used to view and compare waveforms before and after the translation.

The VTRAN® User Interface Utility (VUI® ) is the graphical user interface tool that ties everything together. It was developed specifically for generating VTRAN® and VCAP® command files by presenting a series of "forms" which are used to set up the translation parameters. VUI® provides context-sensitive help for all form fields, interactive syntax checking, and parameter compatibility analysis. The entire translation process may be launched from within the VUI® and the original and target waveforms can also be displayed using DFTView® via the VUI® . For detailed information on these features, see:

The following diagram illustrates how the VUI® is organized.

Identifying Clocks in VCD/EVCD Files using VCAP®

 

The use of VCAP® is entirely optional. All of the information needed by the VUI® to create a VTRAN® command file and run a successful translation can be entered manually into the PROC_Block fields.

Cyclization is controlled by the VTRAN® PROC_Block. The CYCLE value tells how many print-on-change vectors should be collapsed into a cycle vector. It drives both VTRAN® and the VCAP® Analysis feature. It is chosen first. Most often, this value is fundamentally related to the period value of a clock waveform in the Original Vector File. The VCAP® Clock Identifier feature provides the clock related information on all input signal activity and can be used to determine an optimal CYCLE value. It can be used to verify clock behaviour in the simulation results or as an exploration tool when information on device functionality is incomplete. For each selected signal in the simulation data file, VCAP® reports:

  • period length
  • RZ/RO timing behaviour
  • the time of the first and last leading edge in the waveform
  • the longest duration of inactivity
  • the maximum number of consecutive pulses observed
  • total number of pulses
  • comparison between device period and target ATE cycle length

VCAP® reports signal behaviour with the most likely clock candidates listed first. A second section lists those signals that can be disqualified as a device clock signal. Disqualifying characteristics are completely selectable by the user. They can include a change in period length, a change in edge placement, a period value that is too long, inactivity for too many cycles, or a less than acceptable number of consecutive pulses.

The VCAP® Clock Identifier feature can be applied to either single timeset or changing timeset waveforms. Multiple cycle lengths are also supported. Both VUI-VCAP® and VCAP® command line interfaces are presented in this application note.

The VCAP® Command File with the Clock Identifier

Historically, the ASCII command file used by VCAP® has been created using a text editor and VCAP® has been launched from the command line.

vcap command_file_name

Running VCAP® using the command file below, causes the Clock Identifier feature to run with the default settings.

src_block
   begin
      source_FILE = "small.evcd"; {# Analysis is performed on the source_FILE}
      SCRIPT_FORMAT VERILOG_VCD ; {# Selects the VERILOG_VCD canned reader}

      {# VCD/EVCD input formats may require the INPUTS/OUTPUTS/BIDIRECTS and
         even BIDIRECT_CONTROL fields to specify signal direction}
   end;

clock_identifier_block	{# Tells VCAP® to run Clock Identifier Analysis}
   begin			  
      {# Place other Clock Identifier commands here}
   end;
end

The default settings for each CLOCK_IDENTIFIER command are:

  • CHECK_PINS pinlist ; By default, all signals (only input behaviours) are analyzed.
  • ALLOW_MULTIPLE_PERIOD_VALUES; Unless specified, a signal is DISQUALIFIED when a change in period is detected. By default, it is not specified.
  • CYCLE_MIN = n; When set, clock values shorter than 'n' are flagged in the report file. It is used to identify cycle times that are less than the minimum cycle length on the target ATE. By default, it is not specified.
  • MAX_PERIOD_BEHAVIOURS [=] n; If more than n timing behaviours are identified, the signal is DISQUALIFIED. By default this value is 5.
  • MAX_PERIOD_VALUE [=] n; If the period value detected is greater than nns, the signal is DISQUALIFIED. The default value is 100ns.
  • MAX_CLOCK_INACTIVITY [=] n; If the number of consecutive inactive cycles observed in the waveform is greater than 'n', the signal is DISQUALIFIED. By default, this value is not set.
  • MIN_SEQUENTIAL_PULSES [=] n; If the maximum number of consecutive pulses observed is less than 'n', the signal is DISQUALIFIED. The default value is 20.
  • REPORT_FILE [=] "filename"; Specifies the name of the file to which the Clock Analysis Report will be written. If no REPORT_FILE command is given then the default file name is "clockid.rpt".
  • RESOLUTION [=] n; Indicates the number of significant digits after the decimal on times written in the report file. 'n' can be 1.0 (no decimal digits), 0.1 (one digit to right of decimal point), 0.01 (two decimal digits), etc. all the way up to 0.000001 (six decimal digits). The default is to have integer time stamps (n = 1.0).
      For all places where times are specified, time units are ns.

 

An Excerpt of VCAP® Report File

See an excerpt of the report file generated by VCAP® below.

CLOCK ANALYSIS
==============

CLOCK CANDIDATES WITH SINGLE TIMING

-----------------------------------

SigA                        
    First Leading Edge: 60ns Last Leading Edge: 2160ns
    Total Number of Pulses: 33
	Period 60ns PINTYPE RO 0,50 
	Max Consecutive # of Pulses = 30
	Max duration of inactivity = 130ns began at time 1850ns
.
.
.

CLOCK CANDIDATES WITH VARYING EDGE TIMES

----------------------------------------

SigB                        
    First Leading Edge: 20ns Last Leading Edge: 2150ns
    Total Number of Pulses: 72
	Period 30ns
	  PINTYPE RZ 20,30 
	      Max Consecutive # of Pulses = 24    First Instance @ 20ns
	      Total # of Pulses = 48
	      Max duration of inactivity = 0ns

	Period 30ns
	  PINTYPE RZ 5,20 
	      Max Consecutive # of Pulses = 24    First Instance @ 725ns
	      Total # of Pulses = 24
	      Max duration of inactivity = 0ns
.
.
.

DISQUALIFIED_CLOCK CANDIDATES

-----------------------------

SigD                        
    First Leading Edge: 60ns Last Leading Edge: 2160ns Total Number of Pulses: 20
	    DISQUALIFIED: Period value changed at time 180ns 
	Period 60ns
	PINTYPE RO 0,50 
	Period 360ns
	PINTYPE RO 0,350 
.
.
.
Data[0]                      DISQUALIFIED: No pulses detected.
.
.
.

Signals that maintain a consistent period with consistent edge placements are listed under the heading "CLOCK CANDIDATES WITH SINGLE TIMING". On SigA, the period observed by VCAP® is 60ns. The RO format indicates that it is a negative going pulse. The leading and trailing edges relative to the beginning of the waveform are 0ns and 50ns respectively. The maximum duration of inactivity on this signal is 130ns beginning at time 1850ns (i.e. the signal is high from 1850ns to 1980ns). When multiple signals meet the requirements of CLOCK CANDIDATES, signals with shorter period values appear first.

The section with the heading "CLOCK CANDIDATES WITH VARYING EDGE TIMES" is similar in that it includes signals with waveforms that maintain a consistent period length. It is different, in that the leading and trailing edges on these signals vary. In this example, SigB has a consistent period of 30ns. It is a positive going pulse (RZ). The leading and trailing edges are at 20ns and 30ns up until the period beginning at 720ns (725ns - 5ns) where the leading and trailing edges occur at 5ns and 20ns. In this example, up to 5 edge sets are allowed (MAX_PERIOD_BEHAVIOURS = 5). These behaviours may appear once or many times during the waveform. VCAP® reports the first instance (first leading edge) of each behaviour. The Max Consecutive # of Pulses is the largest number of active pulses with this period/edge set that appear in the waveform without stops. The Max duration of inactivity = 0ns means that the signal is active (pulses) in every cycle.

Finally "DISQUALIFIED_CLOCK CANDIDATES" lists those signals that have been analyzed but fail to meet the requirements of a clock signal. In this example, SigD is DISQUALIFIED because VCAP® has determined that its period is not consistent. Period values of 60ns and 360ns are both observed and by default ALLOW_MULTIPLE_PERIOD_VALUES has not been set.

A reasonable CYCLE length value for this translation is 60ns. Other reports may suggest a period value that is the least common multiple of observed period values. Asynchronous signals best handled as free running clocks, may be identified also.

See where this is used in the VTRAN® command file in the next section.

Plugging the Results into VTRAN®

The 60 ns value derived in the previous section should be plugged into the VTRAN® PROC_BLOCK. In single timeset translations, like the EVCD to 93K example below, there are two parameters that are potentially affected.

ovf_block
   begin
      ORIG_FILE = "small.evcd";
      SCRIPT_FORMAT VERILOG_VCD;
   end;

proc_block
   begin
      AUTO_ALIGN 60;			{# cycle = 60 }
      CYCLE = 60;       		{# cycle = 60 }
      PINTYPE RZ2X SigE @ 10, 30, 40, 60 ;
      PINTYPE STB SigF @ 35 ;
      PINTYPE NRZ Data[0] Data[1] Data[2] Data[3] @ 0 ;
      PINTYPE RZ2X SigB @ 20, 30, 50, 60 ;
      PINTYPE RO SigA SigC @ 0, 50 ;
      PINTYPE RZ SigI SigJ @ 50, 55 ;
      PINTYPE RZ SigD @ 50, 60 ; 
      PINTYPE STB SigG SigH @ 37 ;
      STATE_TRANS pure_inputs 'U'->'1', 'D'->'0';
      STATE_TRANS bidir_inputs 'U'->'1', 'D'->'0';
   end;

tvf_block
   begin
      TARGET_FILE = "test.avc";
      TESTER_FORMAT HP93000
         DVC_FILE = "test.dvc"
      ;
      MERGE_BIDIRECTS  10HLMZX;
   end;

In this example, the AUTO_ALIGN cyclization strategy has been used. This strategy is used when the goal is to replicate the timing of the original simulation file. The cycle parameter in AUTO_ALIGN tells VTRAN® to collapse each 60ns section of the Original Vector File into 1 vector cycle in the Target Vector File. The cycle parameter in the CYCLE command, tells VTRAN® that the TVF format should also be based on 60ns tester cycles.

Other single timeset strategies are handled similarly. The clock value derived from the VCAP® Clock Identifier plugs directly into the cycle value of the cyclization command, i.e. AUTO_ALIGN (shown above), ALIGN_TO_CYCLE, and ALIGN_TO_STEP. Depending on the desired target timing, the same cycle may be use to specify the target cycle value.

The VCAP® Timing Analysis feature can be used to automatically provide timing information for the PINTYPE statements if using AUTO_ALIGN or the "PINLIST @ TIME" entries in the ALIGN_TO_CYCLE statement. It is also driven by the cycle parameter used above. See the Application Note titled VTRAN® Guide to VCD/EVCD-to-ATE Translations" (http://www.sourceiii.com/notes-cyclize-vcd-ate.html) for more information on this.

VCAP/VTRAN® from the VUI®

When the Initial Setup Form specifies an Event-based INPUT_FORMAT and a Cycle-based TARGET_FORMAT, the Clock Identifier option is made available for VTRAN® Cyclization Functions on the PROC_Block Form via an 'Analyze Clocks' button.

Note: Verilog VCD/EVCD) INPUT_FORMATs may require the INPUTS/OUTPUTS/BIDIRECTS field on the OVF_Block form to specify signal direction. This can be generated by using the VUI® Signal Editor. This utility automatically reads all available signals from the OVF file and then allows the user to make signal selections and assign signal direction.

Select the Cyclization strategy appropriate for your application and launch the VCAP® Clock Identifier by pressing 'Analyze Clocks'. Follow the prompts to modify the commands, run VCAP®, and then apply the desired clock value to the CYCLE length fields in the VUI PROC_Block form.

See the VUI® User Guide (http://www.sourceiii.com/files/S3bundle/VUI_User_Guide.pdf) for details on navigating the Clock Timing Analysis forms.

Non-default values of Clock Identifier parameters are primarily used to change the criteria for CLOCK DISQUALIFICATION.

Example 1

In this example, a given signal is a DISQUALIFIED_CLOCK CANDIDATE if its clock behaviour changes with respect to either edge placement or period. Note that other default disqualifying criteria still apply.

src_block
   begin
      source_FILE = "small.evcd";
      SCRIPT_FORMAT VERILOG_VCD ;
    end;
clock_identifier_block
   begin
      MAX_PERIOD_BEHAVIOURS = 1;
   end;

Example 2

In this example, only signals SigA and SigB are analyzed. A signal is a DISQUALIFIED_CLOCK CANDIDATE if its clock period is greater than 50ns.

src_block
   begin
      source_FILE = "small.evcd";
      SCRIPT_FORMAT VERILOG_VCD ;
    end;
clock_identifier_block
   begin
      CHECK_PINS SigA, SigB;
      MAX_PERIOD_VALUE = 50;
   end;

Example 3

If ALLOW_MULTIPLE_PERIOD_VALUES; is included in the VCAP® CLOCK_IDENTIFIER block, a change in period does not automatically make a signal a DISQUALIFIED_CLOCK CANDIDATE. This is particularly useful in multiple timeset situations. The results of this analysis can be used to support a TEMPLATE CYCLIZATION strategy. See the Application Note titled "TEMPLATE CYCLIZATION" (http://www.sourceiii.com/notes-temp-cyc.html). Each period/edge combination is considered a period behaviour.

src_block
   begin
      source_FILE = "small.evcd";
      SCRIPT_FORMAT VERILOG_VCD ;
    end;
clock_identifier_block
   begin
      MAX_PERIOD_BEHAVIOURS = 5;
      ALLOW_MULTIPLE_PERIOD_VALUES;
   end;

Example 4

The CYCLE_MIN is associated with the minimum cycle value allowed on the target tester hardware. When specified, this causes VCAP® to generate a warning on a possible hardware violation and a multiplexed timing format is suggested. It does not change how signals are disqualified from the being a CLOCK CANDIDATE.

VCAP® Command File

src_block
   begin
      source_FILE = "small.evcd";
      SCRIPT_FORMAT VERILOG_VCD ;
    end;
clock_identifier_block
   begin
      ALLOW_MULTIPLE_PERIOD_VALUES;
      CYCLE_MIN = 200;
   end;

Report Excerpt

CLOCK CANDIDATES WITH SINGLE TIMING

-----------------------------------

clockB
    First Leading Edge: 80ns Last Leading Edge: 980ns
    Total Number of Pulses: 15
        Period 60ns PINTYPE RO 20,50
        **Warning:Waveform Period, 60ns, may violate the ATE Target Minimum 200ns
                Consider PINTYPE  RO4X 20,50,80,110,140,170,200,230
        Max Consecutive # of Pulses = 15
        Max duration of inactivity = 0ns
.
.
.

Example 5

On a given signal, the clock behaviour may stop and start. Excessive inactivity can, however, indicate that the signal does not provide meaningful cycle information. The threshold is specified with the MAX_CLOCK_INACTIVITY command.

src_block
   begin
      source_FILE = "small.evcd";
      SCRIPT_FORMAT VERILOG_VCD ;
    end;
clock_identifier_block
   begin
	MAX_CLOCK_INACTIVITY = 3; {#DISQUALIFY a signal if it is 
                                    INACTIVE for more than 3 cycles}
   end;

See that in the report excerpt, the actual 'Max duration of inactivity' is reported in ns rather than by number of cycles.

Analyzing Transitions for Non-Standard State Values

Transitions from logic low to logic high and logic high to logic low are considered to be clock edges by VCAP®. Other transition types are not analyzed. VCAP® recognizes logic low as 0 or D and logic high as 1 or U. If different logic low/high state characters appear in the Original Vector File, then the STATE_TRANS should be used in the SRC_Block to map them to these characters. The syntax for this command is:

STATE_TRANS [=] [dir] 'from_state'->'to_state' , . . ;

where from_state is a 1 or 2 character state and to_state is a single character state. dir is either inputs or outputs.

Example

src_block
   begin
      source_FILE = "small.evcd";
      SCRIPT_FORMAT VERILOG_VCD;
      STATE_TRANS inputs 'A'->'0', 'B'->'1' ;
   end;
clock_identifier_block
   begin
      CHECK_PINS clockSigA;
      MAX_PERIOD_VALUE = 200;
      CYCLE_MIN = 200;
      MAX_PERIOD_BEHAVIOURS = 1;
      report_FILE = "rep.rpt";
      resolution = .1;
   end;

This command file causes VCAP® to translate each 'A' and 'B' state found on inputs to '1' and '0' states respectively. The result is that A->B and B->A state transitions are recognized by VCAP® as clock edges.

START and TERMINATE Commands

It is not always appropriate to process the entire Original Vector File. With the START and TERMINATE commands, VCAP® can be told to start/stop loading vectors from the file at a specified times. These commands are part of the SRC_Block and the syntax is:

START TIME [=] n ; 
TERMINATE TIME [=] n ; 

Example:

src_block
   begin
      source_FILE = "small.evcd";
      SCRIPT_FORMAT VERILOG_VCD ;
      START TIME 200;
      TERMINATE TIME 25000;
      end;

PINTYPE offsets values, contained in the report file, are relative to the specified START TIME value. Other reported time values (i.e. First Leading Edge, Last Leading Edge, etc...) are relative to time 0.

Overview

The Clock_Identifier analyzes high to low and low to high transitions. All other edge types are ignored. All the clock characteristics are determined from the first 3 significant edges. They are:

  • Leading Edge Time - The first significant edge
  • Trailing Edge Time - The edge after the leading edge
  • Period - The length of time between successive leading edges
  • PINTYPE - A positive going pulse is RZ. A negative going pulse is RO. For a given signal, the clock Identifier feature assumes this is constant over the entire waveform.
  • Offset Values - The PINTYPE edge offsets are calculated from 0 or the START TIME value. In the case of a single period value, the leading edge offset is the (Leading Edge Time - [Period * floor(Leading Edge Time/Period)]). In the case of multiple period values, the offset is calculated from the end of the last completed period.
  • Inactive Clock Logic Level - RZ pulses have an Inactive Logic Level of 'low'. RO pulses have an Inactive Logic Level of 'high'. Period values during times of inactivity are assumed to be the length of the last period actually measured.

Clock statistics like Total Number of Pulses, Max Consecutive Pulses, and Max duration of inactivity are collected on a per pin basis as the waveform is processed.

The clock identifier feature interprets everything in terms of a clock behaviour, either pulsing or inactive and multiple clock behaviours (i.e. multiple periods lengths and multiple edgesets) on a single pin can be identified and managed. The presence of behaviours other than clock (i.e. extended active times, a change in pulse direction, etc...) can cause unexpected results in the report file. In these cases, it may be useful to run the VCAP® Analysis feature with TRACK_WAVEFORM_CHANGES to better understand the changing behaviour of a signal. Using the START TIME/TERMINATE TIME commands in the SRC_Block can help narrow the focus of the analysis. Looking at waveform using DFTView may also be helpful.

Determination of RZ/RO Format

The first clock transition type determines the active state of the clock. If the first transition on a signal is not logically 0->1 or 1->0, however, VCAP® also skips the next edge if it occurs before the determined period value. In the following example, the first edge, at 40ns, is Z->1 and is skipped because it is not a clock edge. The edge 1->0, at 50ns, is also skipped because it occurs inside the first period as determined by the difference between the first two, like clock edge types. VCAP® determines that the first leading edge occurs at 100ns and the signal to be of type RZ.

If on the other hand, the first non-clock type transition is skipped and both of the next two edges occur before the end of the first period, no clock edge is skipped. In the following example, the signal is also determined to be of type RZ with the first leading edge occurring at 100 ns.

 

Clocks with One Consistent Behaviour

When the Clock Identifier observes signals with a consistent period and edgeset, it reports the stats in the CLOCK CANDIDATES WITH SINGLE TIMING section of the report file.

CLOCK CANDIDATES WITH SINGLE TIMING

-----------------------------------

SigA
    First Leading Edge: 20ns Last Leading Edge: 440ns
    Total Number of Pulses: 8
        Period 60ns PINTYPE RZ 20,50 
        Max Consecutive # of Pulses = 8
        Max duration of inactivity = 0ns
.
.
.

Clocks with One Period and Multiple Edge Sets

When ALLOW_MULTIPLE_PERIOD_VALUES has not been specified and the Clock Identifier observes signals with a consistent period and multiple edgesets, it reports the stats in the CLOCK CANDIDATES WITH VARYING EDGE TIMES section of the report file.

CLOCK CANDIDATES WITH VARYING EDGE TIMES

----------------------------------------

SigA
    First Leading Edge: 20ns Last Leading Edge: 450ns
    Total Number of Pulses: 5
        Period 60ns
          PINTYPE RZ 20,50
              Max Consecutive # of Pulses = 2    First Instance @ 20ns
              Total # of Pulses = 2
              Max duration of inactivity = 220ns began at time 110ns

        Period 60ns
          PINTYPE RZ 30,50
              Max Consecutive # of Pulses = 3    First Instance @ 330ns
              Total # of Pulses = 3
              Max duration of inactivity = 0ns
.
.
.

The statistics for multiple occurrences of the same clock behaviour are combined. Up to MAX_PERIOD_BEHAVIOURS are collected and reported.

Clocks with Multiple Periods and Multiple Edge Sets

When ALLOW_MULTIPLE_PERIOD_VALUES has been specified and the Clock Identifier observes signals with multiple periods and multiple edgesets, it reports the stats in the CLOCK CANDIDATES WITH VARYING PERIODS and EDGE TIMES section of the report file.

CLOCK CANDIDATES WITH VARYING PERIODS and EDGE TIMES

----------------------------------------------------

SigA
    First Leading Edge: 20ns Last Leading Edge: 470ns
    Total Number of Pulses: 6
        Period 60ns
          PINTYPE RZ 20,50
              Max Consecutive # of Pulses = 2    First Instance @ 20ns
              Total # of Pulses = 2
              Max duration of inactivity = 0ns

        Period 80ns
          PINTYPE RZ 30,70
              Max Consecutive # of Pulses = 3    First Instance @ 150ns
              Total # of Pulses = 4
              Max duration of inactivity = 120ns began at time 350ns

Up to MAX_PERIOD_BEHAVIOURS are collected and reported.

DISQUALIFIED: PINTYPE offsets are inconsistent with the Period Value

If the Clock Identifier detects an inconsistency between the edge offset and the period value, it is flagged in the report file. See the example waveform below.

The first 2 pulses are correctly identified with Period 60ns and PINTYPE RZ 20,50. Then the period changes. The new period is determined to be 260ns. The offset values, PINTYPE RZ 30,280 are calculated from the end of the last completed period, at 120ns. The second offset occurs beyond the period boundary. In reality, the format of the signal has changed to NRZ or RO. VCAP® identifies this problem with "DISQUALIFIED: PINTYPE offsets are inconsistent with the Period Value" in the report file.

.
.
.
DISQUALIFIED_CLOCK CANDIDATES

-----------------------------

clockSigA
    First Leading Edge: 20ns Last Leading Edge: 1410ns Total Number of Pulses: 4
        Period 60ns
        PINTYPE RZ 20,50
              Max Consecutive # of Pulses = 2    First Instance @ 20ns
              Total # of Pulses = 2
              Max duration of inactivity = 0ns
        Period 260ns
        PINTYPE RZ 30,280
              Max Consecutive # of Pulses = 1    First Instance @ 150ns
              Total # of Pulses = 1
              Max duration of inactivity = 0ns
            DISQUALIFIED: PINTYPE offsets are inconsistent with the Period Value
.
.
.

 

 

Product Support