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VTRAN was designed to fit into several vector translation flows. Converting STIL or WGL files from ATPG tools into test programs, or going directly from simulation VCD dump files to ATE, VTRAN can handle the task simply and cost-effectively. It also is able to validate these test programs via a playback or VirtualTest ReadBack translation prior to loading onto your tester. The following VTRAN conversion flow charts highlight several common applications where VTRAN can be employed.
| VTRAN® Conversions |  |
CONVERT ATPG-GENERATED WGL & STIL FILES to ATE |
VTRAN greatly simplifies the translation of ATPG-generated WGL or STIL files to a wide variety of Test Equipment. These translations include support for multiple timesets and scan data syntax. Optional processing that can be performed by VTRAN are scaling of timing, delete signals, add signals with complex state equations, mask signals, compression with repeats or loops, expansion of scan, expansion of repeats or loops, file merging and concatenation, insertion of comments or new statements, changing signal names, and many other options.
For more information on using VTRAN for this flow, see the Tester Specific App Notes at:
Also for more general information on VTRAN including the Vtran User's Guide, visit:
| VTRAN® Conversions | |
CONVERT WGL, STIL and Test Programs to VERILOG or VHDL TESTBENCH |
Translating WGL, STIL or previously VTRAN-generated Test Programs to a Verilog or VHDL testbench is often a time and cost saving step. Before loading the Test Programs onto a physical device tester, or before using the WGL or STIL files in down-stream flows, it is very advantageous to validate them by first translating them to a Validation Testbench for simulation. VTRAN provides this capability for both Verilog and VHDL environments.
For more information on using VTRAN for this flow, see the Tester Specific App Notes at:
Also for more general information on VTRAN including the Vtran User's Guide, visit:
| VTRAN® Conversions | |
CONVERT VERILOG VCD/EVCD FILES to ATE, WGL, or STIL with READBACK VALIDATION FLOW |
VTRAN greatly simplifies the translation of Verilog or VHDL Simulation-generated VCD or EVCD files to a wide variety of Test Equipment. These translations include support for multiple timesets and involve the cyclization of the print-on-change vectors into cycle-based vectors for ATE. Optional processing that can be performed by VTRAN are scaling of timing, delete signals, add signals with complex state equations, mask signals, compression with repeats or loops, file merging and concatenation, insertion of comments or new statements, changing signal names, and many other options. The VTRAN ReadBack (playback) flow provides a means of validating the Test programs prior to loading it onto a tester.
For more information on using VTRAN for this flow, see the Tester Specific App Notes at:
Also for more general information on VTRAN including the Vtran User's Guide, visit: