Simulate Translate Test

Translating WGL/STIL Vector Files to HP83000/93000 Tester Formats

The most common vector formats produced by today's leading ATPG tools are WGL and STIL. The WGL format syntax was originally developed by TSSI and has become somewhat of a defacto industry standard. Virtually all ATPG tools in use today can generate vectors in this format (although not all follow the syntax strictly). STIL (Standard Test Interface Language) is a recently IEEE-adopted standard format for test vectors that is growing in use. Many ATPG tools offer the user the option of generating vector files in either of these two formats. This Application Note focuses on the task of translating vector files in these formats to test programs for the HP83000 and 93000 testers (the actual ASCII vector data formats are the same for both testers).

Overview

Vtran makes the task of translating WGL and STIL files into HP83000/93000 test programs relatively simple. Canned readers for both of these formats are included with the vtran product bundle. As long as the WGL and STIL files follow the syntax of their respective specifications, the readers can easily handle them. If the WGL file is being generated from the Synopsys TetraMAX ATPG tool, then it is important to make sure that the option settings are such that they produce a syntactically and semantically correct WGL file. A number of the user-controlled options will result in an invalid WGL file. The option settings currently recommended for TetraMAX are as follows:

  set wgl -bidi_map -x -x
  set wgl -bidi_map z- z-
  set wgl -bidi_map 0x 0x
  set wgl -bidi_map 1x 1x
  set wgl -bidi_map xx xx
  set wgl -bidi_map z0 z0
  set wgl -bidi_map z1 z1
  set wgl -bidi_map zx zx
  set wgl -bidi_map zz zz
  set wgl -chain_list shift
  set wgl -group_bidis
  set wgl -inversion_reference master
  set wgl -last_scan
  set wgl -nomacro
  set wgl -nopad
  set wgl -pre_measured
  set wgl -scan_map dash

These settings are applicable to TetraMAX version 2.02 and later. See also the online help notes within the TetraMAX environment.

For STIL vector files, the optional "ScanStructures" block must be present. The information contained in this block is needed by the reader to fully maintain the scan data during translation to the tester formats.

The vector translation process is divided into three separate tasks or blocks, which correspond to the three blocks in the vtran command file - the OVF_BLOCK, the PROC_BLOCK and the TVF_BLOCK. The commands and parameters in these blocks direct the details of the translation. In general, the OVF_BLOCK contains information necessary for vtran to read the input file or "Original Vector File" (i.e. the WGL or STIL file). The PROC_BLOC contains commands that tell vtran what data processing functions you want performed on the simulation data during translation. These typically would be instructions such as how you would like state characters mapped between the input and output formats, or perhaps some desired signal masking. For both of these cycle-based formats, there is not very much processing that needs to be done so the OVF_BLOCK and PROC_BLOCK are typically small. Finally, the TVF_BLOCK contains commands that specify the desired output format - in this case it is the HP format for either the HP83000 or HP93000 testers. There may also be some final processing to be done or some optional user-supplied parameters that appear in the TVF_BLOCK. Now, let's take a look at some specifics for these translations.

The OVF_BLOCK

When using the vtran WGL or STIL canned reader, there is actually very little information (in the way of command instructions) needed by vtran to read the data and do any necessary mapping of state characters, in preparation for generating the HP test vector file. In fact, the only command required in the OVF_BLOCK would be a "TABULAR_FORMAT" command, which might look like:

OVF_BLOCK
   BEGIN
   TABULAR_FORMAT wgl -cycle, -scan;
   END

When reading STIL files, simply replace the "wgl" with "stil". If the name of the cycle-based file is being supplied from the command line, then this is all that is needed in the OVF_BLOCK. Otherwise we might add the ORIG_FILE command to this block:

OVF_BLOCK
   BEGIN
   TABULAR_FORMAT wgl -cycle, -scan;
   ORIG_FILE = "filename";
   END

Note the two flags that are being passed to the readers. The first flag (-cycle) is required and tells the reader to not flatten-out the timing in the input file. Since the HP test vector files are cycle-based formats (as are WGL and STIL), this flag instructs the reader to keep the signal timing information separate from the cycle vector data. The second flag (-scan) is optional. If there is no scan data in the input files, then this flag does nothing and could hence be left out. If the input WGL or STIL vector files do contain scan data, then this flag instructs the reader to maintain this scan data as separate data structures, to be passed to the HP-formatted vectors as scan data. In general, this is a desirable thing to do since the resulting vector files are usually significantly smaller using scan syntax than without it. If, however, the user wishes the scan data contained in the input WGL or STIL files to be expanded into normal sequential vectors in the HP test vector files, then this flag can be omitted. It is normally recommended that both of these flags be used.

The PROC_BLOCK

The PROC_BLOCK commands required for translating WGL or STIL files to HP83000/93000 tester files will depend on which input file format is being read, and on how the state characters have been defined for the HP testers . If we are mapping WGL state characters to those needed for HP83000/93000, then a typical mapping might look like:

PROC_BLOCK
   BEGIN
   STATE_TRANS pure_inputs '-'->'0', 'X'->'0';
   STATE_TRANS bidir_inputs '-'->'Z';
   STATE_TRANS outputs '0'->'L', '1'->'H',
        '-'->'X', 'Z'->'M';
   END

These HP83000/93000 state characters are consistent with those commonly used and match the defaults used by vtran when generating an optional DVC file (described later). This state mapping is only suggested. It accomplishes two things - first it maps WGL state characters to their equivalent default HP characters, and second it maps any undefined states on input pins to logic 0 (to avoid any floating inputs). The user may wish to modify these to achieve some other desired behavior, or if a custom DVC file is being used which defines other state characters. Mapping the state characters from a STIL file takes a bit more work:

PROC_BLOCK
  BEGIN
  STATE_TRANS pure_inputs 'U'->'1', 'D'->'0', '?'->'0';
  STATE_TRANS bidir_inputs 'U'->'1', 'D'->'0', '?'->'Z';
  STATE_TRANS outputs 'T'->'X', 'x'->'X','l'->'L',
      'h'->'H', 't'->'X', 'R'->'L', 'G'->'H',
      'Q'->'X', '?'->'X';
  END

Here we need to be careful about how we map the numerous state characters in a STIL file to those being used by the HP testers. Again, this is only a suggested mapping, the user may want to modify this for different behavior.

The TVF_BLOCK

There is really only one command required in the TVF_BLOCK of the vtran command file for the generation of an HP83000/93000 vector file. This is the TESTER_FORMAT (or SIMULATOR) command, which specifies the target vector file format. The syntax for this command (and the optional [ ] parameters) is:

SIMULATOR HP83000 { or HP93000 }
    [, -DISABLE_REPEATS]
    [, -AUTO_GROUP ]
    [, SCANIN_DEFAULT="0"]
    [, USE_TIMESET="tset"]
    [, MAX_LINE_LENGTH="nn"]
    [, REPEAT_THRESHOLD = "nn"]
    [, TIME_STAMPS = "ON" | "OFF"]
    [, AUTO_SCAN_PINS_IN = "pin"]
    [, AUTO_SCAN_PINS_OUT = "pin"]
    [, DVC_FILE="fname"]
    [, CONFIG_FILE="fname"] { not currently used }
    ;

While translating WGL or STIL vectors to HP tester formats, vtran will automatically look for vectors that are repeated in the vector stream, and optionally use the Repeat function to minimize vector file size. This activity can be disabled using the -DISABLE_REPEATS flag. The REPEAT_THRESHOLD parameter can also be used to control how many successive identical vectors will cause the Repeat function to be activated - the default is 2. For example, if we set the REPEAT_THRESHOLD to "10", whenever 10 or more successive vectors are identical, then the Repeat function would be used to collapse them. The -AUTO_GROUP flag causes vtran to try and organize the signals into groups for legibility using a simple algorithm. When padding unequal length scan chains, the default pad character is '0', but this can be modified with the SCANIN_DEFAULT parameter. The USE_TIMESET parameter is used primarily when translating print-on-change vectors where there is no timing information being provided in the vector file - it is not normally used when translating WGL or STIL files where this information is provided. The MAX_LINE_LENGTH parameter can be used to specify the maximum number of characters per line in the HP vector file - the default is 80.

For debugging and analysis, it is often useful to see the timestamps for each vector in the test program that corresponds to its cycle time in the WGL or STIL input file. These timestamps are displayed as comments in the output file, but can be disabled using the TIME_STAMPS = "OFF" parameter. When translating vectors from a source which does not explicitly have scan vectors defined but may have scan activity imbedded in them (this might happen in a VCD input file), then the AUTO_SCAN_PINS_IN and AUTO_SCAN_PINS_OUT parameters can be used to tell the HP testers to try using AUTO_SCAN mode to extract the scan activity. These parameters are not normally used with WGL or STIL files from an ATPG tool.

The DVC file will only be created if the DVC_FILE parameter is specified with a file name. The pin timing in this file is expressed in terms which are relative to the CYCLE time (period) of the vectors. The interface supports multiple timesets. For scan chains, all chains are grouped into a single scan_template and are defined with scan lengths equal to the longest chain. During scan operations, scan chains which are shorter get padded appropriately.

Some Examples

This first example illustrates the translation of a WGL file to HP83000 vector file. This WGL file happens to contain some scan vector data. Any input pins that are undefined in the WGL file are being mapped to a logic '0' in the test program. A timing file is being generated in "s2.dvc".

ovf_block
     begin
     orig_file "s2.wgl";
     tabular_format wgl -cycle, -scan ;
     end
proc_block
     begin
     disable_vector_filter;
     STATE_TRANS pure_inputs '-'->'0', 'X'->'0';
     STATE_TRANS bidir_inputs '-'->'Z';
     STATE_TRANS outputs '0'->'L', '1'->'H',
        '-'->'X', 'Z'->'M';
     end
tvf_block
     begin
     tester_format hp83000 -auto_group,
      SCANIN_DEFAULT = "1",
      DVC_FILE="s2.dvc",
      REPEAT_THRESHOLD = "32",
      ;
     target_file = "s2.83000";
     end;
end;

This next example illustrates the translation of a STIL vector file with scan data, to an HP93000 tester format. As indicated above, the state translations are a bit more complicated since there are more potential states in the STIL file. The state translations shown assume the typical HP93000 state characters are being used. Here we are also generating a timing file. Each vector line is limited to 64 characters in length to make the file more easily readable and printable.

ovf_block
  begin
  tabular_format stil -cycle -scan;
  orig_file = "s6.stil" ;
  end;
proc_block
  begin
  state_trans pure_inputs 'D'->'0', 'U'->'1', '?'->'0';
  state_trans bidir_inputs 'D'->'0', 'U'->'1', '?'->'X';
  state_trans outputs 'T'->'X', 'x'->'X',
    'l'->'L', 'h'->'H', 't'->'X', 'R'->'L',
    'G'->'H', 'Q'->'X', '?'->'X';
  end;
tvf_block
  tester_format HP93000
    -AUTO_GROUP,
    DVC_FILE = "s6.tms",
    MAX_LINE_LENGTH = "64",
    TIME_STAMPS = "OFF"
    ;
  target_file = "s6.hp93";
  end;
end;

Product Support

Customer Quotes

  • We currently use VTRAN for translating WGL, EVCD and VCD vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
  • Sanera Utilizes Full Featured VTRAN® to Convert Functional and ATPG Vectors "We chose VTRAN® because it can handle multiple simulation file formats (including VCD and WGL) from a single tool. VTRAN's commands are easy to use. The flexibility in pin mapping, masking outputs, and generating scan-based vectors proves to be tremendously helpful. And most of all, Source III provides excellent, fast response to our support needs. This helps us to get things moving very quickly - making good solid progress." Ken ChenTest Engineering Manager
  • We use VTRAN® to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly.
  • VTRAN® is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with Source III has been positive and their support is extremely responsive and timely.
  • Source III VTRAN® tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion
  • Intrinsix Uses VTRAN® to Speed Vector Translation Flow "I had one customer who used VHDL for RTL, Verilog for gate level simulation, and sometimes used EPIC tools. Getting vectors into the various formats was a nightmare. VTRAN® made the translation process easy and seamless. Plus, WGL or STIL for the test group. Support from Source III has also been quite impressive. In one case, they wrote a bug fix for me in under a day." John Weiland Intrinsix Consultant  
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