Your source for: Test vector translation, translate WGL vectors, Translation paths between popular simulation, ATPG and tester vector formats, WGL to test,
Translate STIL vectors
, STIL to ATE, STIL to test, Simulation to test, ATPG to test, Translate VCD to ATE, VCD to test, Verilog testbench translation, WGL waveform display, STIL waveform display.

Popular VTRAN™ Translations

VTRAN™ Release 9.5 Translators

The 9.5 Release of VTRAN™ supports numerous translation paths between popular simulation, ATPG and tester vector formats. Included in this is support for the handling of scan data, as well as multiple timing sets. Scan data support is particularly important for vector files created by many of the scan insertion, BIST and other ATPG programs on the market today. The following matrix summarizes the availability of canned readers and writers for some of the more popular translation paths. The Support column indicates, for cycle-based formats, whether VTRAN™ supports scan, loop or repeat syntax. For those testers that do not indicate scan or loop support, VTRAN™ will automatically flatten any of these structures that may have been in the input file before translation. VTRAN™ can translate any format for which a Reader module exists to any format for which a Writer module exists. Please note that this list is not exhaustive, it merely highlights some of the more popular formats - see VTRAN™ User's Guide Appendix C, D and E for a complete listing.

VTRAN™ provides many powerful facilities for performing these translations which can vary significantly in complexity and user involvement. Translations from cycle-based formats like WGL, STIL (IEEE Standard 1450-1999) or TDL_91 to either simulator or tester formats typically are straightforward and require very little input from the user. On the other hand, for translations from event-based formats like Verilog VCD/EVCD format to simulators/testers, the user must provide information about pin directions and timing since this information is not contained explicitly in the VCD vector file itself. Translations from VCD to any of the cycle-based formats (all of the tester formats) will also require the use of one of the ALIGN processes, or the TEMPLATE_CYCLIZATION process to cyclize the event-based data. For additional information on these, and other format translations, together with examples, see the INTERFACES directory which can be downloaded from the Download web page. Also, check our Application Notes web page.

Vector Format Translation Matrix

Formats Support Reader Writer
Simulator Formats
VCDYesYes
EVCDYesYes
nanosimYesYes
LSIMYesYes
Verilog TestbenchNoYes
VHDL TestbenchNoYes
HSIMYesYes
QSIMYesYes
SPICENoYes
Novas FSDBYesNo
ATPG and EDA Formats
WGLscan, loops, repeatsYesYes
STILscan, loops, repeatsYesYes
TDL_91scan, loops, repeatsYesYes
TSTL2scan, loops, repeatsYesYes
FTDLscan, loops, repeatsYesYes
Tester Formats
SVF (JTAG) YesYes
Chromascan, loops, repeatsYesYes
Credence SWAVscan, loops, repeatsYesYes
Teradyne J750scan, loops, repeatsYesYes
Teradyne J971/3scan, repeatsYesYes
Teradyne Catalystscan, loops, repeatsYesYes
Teradyne FLEX+scan, loops, repeatsYesYes
Agilent 93000scan, loops, repeats, XMODEYesYes
IMS MEM Formatscan, repeatsYesYes
LTXscan, repeatsYesYes
Advantest T66xx T3xxscan, loops, repeatsYesYes
Advantest T2000scan, loops, repeatsYesYes
ITS9000scan, repeatsNoYes
PCF (HP3070)YesYes
Q-Star IDDQ/ISSQControl InsertionYes

About Source III

Source III's Simulation and Test Data Management tools focus on the creation, translation and analysis for vector data used or generated by logic simulators, ATPG and ATE. Our premier product, VTRAN, links simulation/ATPG vector data to ATE and other CAE tools. VGEN provides a high-level language for quick and easy creation of simulation vector data, and VCAP performs verification/analysis of simulation data files. All Source III products are supported on Sun Solaris SPARC, Solaris X86 and Linux platforms (32 and 64-bit).

  • VTRAN - a program which reads the state/time information from simulation or ATPG-generated data files, performs some optional processing on this data and then re-formats it for any of over 30 popular logic simulators and ATE. A powerful link between CAE and Test.
  • VCAP - comprehensive simulation data comparison and analysis program.
  • VGEN - a stimulus generation language which reduces the time required to create, modify, document, and maintain simulation stimulus files by up to 80%.
  • DFTView - a powerful interface tool which connects high-level test languages WGL and STIL to popular graphical waveform display tools, enabling users to see, edit and validate the actual waveforms described in the test languages.