Simulate Translate Test

Popular VTRAN™ Translations

VTRAN™ Release 10.1 Translators

The 10.1 Release of VTRAN™ supports numerous translation paths between popular simulation, ATPG and tester vector formats. Included in this is support for the handling of scan data, as well as multiple timing sets. Scan data support is particularly important for vector files created by many of the scan insertion, BIST and other ATPG programs on the market today.

The following matrix summarizes the availability of canned readers and writers for some of the more popular translation paths. The Support column indicates, for cycle-based formats, whether VTRAN™ supports scan, loop or repeat syntax. For those testers that do not indicate scan or loop support, VTRAN™ will automatically flatten any of these structures that may have been in the input file before translation. VTRAN™ can translate any format for which a Reader module exists to any format for which a Writer module exists. Please note that this list is not exhaustive, it merely highlights some of the more popular formats - see VTRAN™ User's Guide Appendix C, D and E for a complete listing.

VTRAN™ provides many powerful facilities for performing these translations which can vary significantly in complexity and user involvement. Translations from cycle-based formats like WGL, STIL (IEEE Standard 1450-1999) or TDL_91 to either simulator or tester formats typically are straightforward and require very little input from the user.

On the other hand, for translations from event-based formats like Verilog VCD/EVCD format to simulators/testers, the user must provide information about pin directions and timing since this information is not contained explicitly in the VCD vector file itself. Translations from VCD to any of the cycle-based formats (all of the tester formats) will also require the use of one of the ALIGN processes, or the TEMPLATE_CYCLIZATION process to cyclize the event-based data.

For additional information on these, and other format translations, together with examples, see the INTERFACES directory which can be downloaded from the Download web page. Also, check our Application Notes web page.

Vector Format Translation Matrix

Formats Support Reader Writer
Simulator Formats
VCD   Yes Yes
EVCD   Yes Yes
nanosim   Yes Yes
LSIM   Yes Yes
Verilog Testbench   No Yes
VHDL Testbench   No Yes
HSIM   Yes Yes
QSIM   Yes Yes
SPICE   No Yes
Novas FSDB   Yes No
ATPG and EDA Formats
WGL scan, loops, repeats Yes Yes
STIL scan, loops, repeats Yes Yes
TDL_91 scan, loops, repeats Yes Yes
TSTL2 scan, loops, repeats Yes Yes
FTDL scan, loops, repeats Yes Yes
Tester Formats
SVF (JTAG)   Yes Yes
Chroma scan, loops, repeats Yes Yes
Credence SWAV scan, loops, repeats Yes Yes
Teradyne J750 scan, loops, repeats Yes Yes
Teradyne J971/3 scan, repeats Yes Yes
Teradyne Catalyst scan, loops, repeats Yes Yes
Teradyne FLEX+ scan, loops, repeats Yes Yes
Agilent 93000 scan, loops, repeats, XMODE Yes Yes
IMS MEM Format scan, repeats Yes Yes
LTX scan, repeats Yes Yes
Advantest T66xx T3xx scan, loops, repeats Yes Yes
Advantest T2000 scan, loops, repeats Yes Yes
ITS9000 scan, repeats No Yes
PCF (HP3070)   Yes Yes
Q-Star IDDQ/ISSQ Control Insertion   Yes

Product Support