Simulate Translate Test

Translating TetraMAX-generated STIL files containing Free Running Clocks

This application note focuses on the translation of TetraMAX generated STIL files that contain free running clocks, specified through use of the UserKeyword FreeRunning. VTRAN® has the ability to translate the free running clock information for use with the Teradyne FLEX/J750+, HP83000, and HP93000 tester formats.

STIL File Overview

TetraMAX generated STIL files indicate asynchronous free running clocks (FRC) through the use of a UserKeyword, FreeRunning. Each free running clock is then listed in the SignalGroups section with an attribute of 'FreeRunning'. Following the attribute (indicated by the UserKeyword) are the values for the clock.

The free running clock patterns may be listed with the main pattern in a ParallelPatList. The patterns all start synchronously through the use of the argument SyncStart. The FRCs are all assigned the argument Extend so that all patterns end at the same time.

TetraMAX STIL file excerpt:

    Signals {
        sig1 In;
        sig2 In;
        clk1 In;
        clk2 In;
    }

    UserKeywords FreeRunning;

    SignalGroups {
        Group1 = 'sig1' + 'sig2';
        _ref_clk1 = 'clk1' { FreeRunning { Period '6400ps';
                                           LeadingEdge '0ps';
                                           TrailingEdge '3200ps';
                                           OffState D;
                                         }
                           }
        _ref_clk2 = 'clk2' { FreeRunning { Period '12800ps'
                                           LeadingEdge '0ns';
                                           TrailingEdge '6800ps';
                                           OffState D;
                                         }
                           }
    }

    PatternBurst "_burst_" {
        ParallelPatList SyncStart {
            "_pattern_" {}
            "_pattern_ref_clk1" {Extend; }
            "_pattern_ref_clk2" {Extend; }
        }
    }

ParallelPatList Usage

A ParallelPatList containing the main pattern and the free running clock patterns may be included in the STIL file but it is not required. If one is used, it is assumed that the first pattern listed is the main pattern and all that follow are free running clock patterns. The main pattern will be the only one read by the VTRAN® STIL reader.

    PatternBurst "_burst_" {
      ParallelPatList SyncStart {
        "_pattern_" { }
        "_pattern_ref_clk0" { Extend; }
        "_pattern_ref_clk1" { Extend; }
        "_pattern_ref_clk2" { Extend; }
        "_pattern_ref_clk3" { Extend; }
      }
    } 

Multiple Clocks in Group

Signal groups may contain more than one signal. The free running clock attributes will be assigned to each signal in the group but the signals will not be treated as a group.

    SignalGroups  {
      Group_1 = 'sig1 + sig2 + sig3';
      _ref_clk2 = 'clk2 + clk3' { FreeRunning { Period '12800ps';
                                                LeadingEdge '6400ps';
                                                TrailingEdge '12800ps';
                                                OffState D;  }}
     }

Overview

Free running clock information is valid only for Teradyne FLEX/J750+, HP83000, and HP93000 tester formats. Free running clock information translated for the Teradyne formats is integrated into the output files. Translations for the HP format will result in a set of avc and dvc output files for each FRC. However, FRCs that share the same period will be combined into one set of avc and dvc files. These sets of files can then be loaded onto the tester using the multiport feature.

The vector translation process is divided into three separate tasks or blocks, which correspond to the three blocks in the vtran command file - the OVF_BLOCK, the PROC_BLOCK and the TVF_BLOCK. The commands and parameters in these blocks direct the details of the translation. In general, the OVF_BLOCK contains information necessary for vtran to read the input file or "Original Vector File" (i.e. the STIL file). The PROC_BLOCK contains commands that tell vtran what data processing functions you want performed on the simulation data during translation. These typically would be instructions such as how you would like state characters mapped between the input and output formats, or perhaps some desired signal masking. Finally, the TVF_BLOCK contains commands that specify the desired output format - in this case it is the HP format for either the HP83000 or HP93000 testers or the Teradyne format for the FLEX or J750+ testers. There may also be some final processing to be done or some optional user-supplied parameters that appear in the TVF_BLOCK. Now, let's take a look at some specifics for these translations.

The OVF_BLOCK

The VTRAN®STIL canned reader does not need any special commands to process the FRC information in the STIL file. A simple OVF_BLOCK processing the STIL file might look like:

    ovf_block
     begin
       tabular_format stil
         -cycle,
         -scan
       ;
       ORIG_FILE = "input.stil";
    end; 

Note the two flags that are being passed to the reader. The first flag (-cycle) is required and tells the reader to not flatten-out the timing in the input file. Since the HP and Teradyne test vector files are cycle-based formats (as is STIL), this flag instructs the reader to keep the signal timing information separate from the cycle vector data. The second flag (-scan) is optional. If there is no scan data in the input files, then this flag does nothing and could be left out. If the input STIL vector file does contain scan data, then this flag instructs the reader to maintain this scan data as separate data structures, to be passed to the tester-formatted vectors as scan data. In general, this is a desirable thing to do since the resulting vector files are usually significantly smaller using scan syntax than without it. If, however, the user wishes the scan data contained in the input STIL file to be expanded into normal sequential vectors in the test vector files, then this flag can be omitted. It is normally recommended that both of these flags be used.

Turn off processing of Free Running Clocks

The VTRAN® STIL reader will always attempt to process free running clocks whenever the UserKeyword FreeRunning is found. To disable this processing, use -ignore_frc.

    tabular_format stil
        -cycle,
        -scan,
        -ignore_frc
    ;

The PROC_BLOCK

The process block contains information such as state character mapping VTRAN® should use for the desired tester format. A PROC_BLOCK containing a typical mapping needed to translate STIL to an HP tester format might look like:

    proc_block
      begin
     state_trans pure_inputs 'U'->'1', 'D'->'0', '?'->'0';
     state_trans bidir_inputs 'U'->'1', 'D'->'0', '?'->'Z';
     state_trans outputs 'T'->'X', 'x'->'X','l'->'L', 'h'->'H',
             't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X';
    end

A PROC_BLOCK containing a typical mapping for a Teradyne tester might look like:

    proc_block
      begin
        state_trans pure_inputs 'U'->'1', 'D'->'0', '?'->'0';
        state_trans bidir_inputs 'U'->'1', 'D'->'0', '?'->'X';
        state_trans outputs 'T'->'X', 'x'->'X','l'->'L', 'h'->'H',
        't'->'X', 'R'->'L', 'G'->'H', 'Q'->'X', '?'->'X';
      end

These are only suggested mappings. The user should modify this as needed for their situation.

The TVF_BLOCK

A suggested TVF_BLOCK to process the STIL file for an HP tester format might look like:

    tvf_block
      begin
        tester_format HP93000
          DVC_FILE  = "short.dvc"
        ;
        target_file  = "short.avc";
        OPTIMIZE_TIMING;        {# remove unused/duplicate tsets}
        ALIAS_TSET _multiclock_capture_WFT_ = tset ;
      end;

A TVF_BLOCK for a Teradyne tester format might look like:

    tvf_block
      begin
          tester_format teradyne
          -flex,
          -basic_timing,
        ;
        target_file  = "short.flex";
        OPTIMIZE_TIMING;
        ALIAS_TSET _multiclock_capture_WFT_ = tset ;
      end;

The OPTIMIZE_TIMING flag should be set so that any unused timesets (namely the FRC timesets) will be removed from the main pattern block of the STIL file. Free running clocks may have timesets that are included in the main PatternBlock.  Once the vtran code processes the free running clocks, those timesets are no longer used but are still sent to the output ATE timing.  They should be removed with the OPTIMIZE_TIMING flag. The ALIAS_TSET provides additional control of the timeset names.

Adding Additional Free Running Clocks

Free running clocks may also be added to the tester output files through the TVF_BLOCK with a FreeRunningClock statement. FRCs that are added through the TVF_BLOCK will override any matching FRCs from the STIL file.

This statement takes the format of:

    FreeRunningClock [input|bidirect], RO|RZ, clockName, clockPeriod, t1, t2;

It is used outside of the tester statement. An example of its use looks like:

    tvf_block
      begin
        tester_format HP93000
           DVC_FILE  = "short.dvc"
        ;
        FreeRunningClock input RZ, new_clk, 6.400, 1.200, 6.400 ;
        target_file  = "short.avc";
        OPTIMIZE_TIMING;        {# remove unused/duplicate tsets}
        ALIAS_TSET _multiclock_capture_WFT_ = tset ;
      end;

Additional information about using the FreeRunningClock statement in the TVF_BLOCK may be found in Appendix D of the VTRAN® User Guide, for Tester Interfaces HP83000/HP93000 (Agilent/Verigy/Advantest) and Teradyne.

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