Simulate Translate Test

Translating EDA Vector Files to SPICE

This application note focuses on the translation of vectors from a variety of well known EDA files to Piecewise Linear source (PWL) data statements usable by the SPICE analog simulator. The PWL data statements are relevant to input stimulus only. For each input, VTRAN® creates a voltage source and a waveform description (PWL) that reflects the pin transitions described in the EDA files. Specific information on the translation of Verilog VCD/EVCD, WGL, and STIL files is provided. Translating other EDA files will typically require similar strategies and processing.

Overview

VTRAN® contains a number of features that enhance the task of generating SPICE source data from EDA simulation data files. First of all, VTRAN's reader technology enables it to efficiently collect data for each time there is a state change on any pin. For SPICE Interfaces, VTRAN® provides a Technology File where the user can specify MIN, TYP, and MAX SPICE specific parameters per technology. The user has full control over the node names and nodes numbers contained in the target SPICE file. Additionally, the VTRAN® SPICE Interface supports the generation of Piecewise Linear continuous analog voltages.

The translation process is divided into three separate tasks or blocks, which correspond to the three blocks in the VTRAN® command file - the OVF_BLOCK, the PROC_BLOCK and the TVF_BLOCK. The commands and parameters in these blocks direct the details of the translation. In general, the OVF_BLOCK contains information necessary for VTRAN® to read the input file or "Original Vector File" (i.e. the Verilog VCD file). The PROC_BLOC contains commands that tell VTRAN® what data processing functions you want performed on the simulation data during translation. Finally, the TVF_BLOCK contains commands that specify the desired output format - in this case it would be SPICE.

THE OVF_BLOCK

When using a VTRAN® canned reader to read an EDA file, like Verilog EVCD, WGL, and STIL, only the format information is really needed in the OVF_BLOCK. Verilog VCD files also require pin declarations.

Verilog VCD/EVCD Format

The"SCRIPT_FORMAT" command defines the actual format of the vector data to be read. When specifying the format with this command, there are two options available:

   SCRIPT_FORMAT Verilog_vcd;

      Or

   SCRIPT_FORMAT Verilog_vcd_f;

The difference between these two options has to do with the signal name hierarchy contained in the VCD file. If the Verilog_vcd option is used, then all of the hierarchy is removed from the signal names, whereas if the Verilog_vcd_f option is used then the module hierarchy is maintained as part of the name. For example, using the first option a signal might be named "dlatcha", whereas using the second option it might be named "top.ram_module.dlatcha". In general, it is usually easier to use the Verilog_vcd option so this is preferred. However, if the low-level signal names in the VCD file are used in more than one place - say in different instantiations of the same module in the design, then it may be necessary to use the Verilog_vcd_f option and refer to signals with their full hierarchical name to distinguish one from the other.

WGL/STIL Format

For WGL and STIL, the "TABULAR_FORMAT" command defines the format of the vector data to be read.

   TABULAR_FORMAT wgl;

      Or

   TABULAR_FORMAT stil;

Pin Declaration

The second set of information needed in the OVF_BLOCK for standard Verilog VCD files is the names and directions of the signals you wish to have read from the file. Often times, VCD files will contain vector information for many more signals than just those that you wish to have read and translated. It is only necessary to specify those in which you are interested. For SPICE targets, only stimulus signals are processed. Stimulus signals are inputs and the input contributor of bidirectional pins. Note, however, that output pins used to determine the direction of bidirectional signals (see THE PROC_BLOCK) must also be specified. The OVF_BLOCK commands necessary to accomplish this are the INPUTS, OUTPUTS, and BIDIRECTS commands. When processing VCD with the format and pin declarations, the OVF_BLOCK may look something like:

  OVF_BLOCK

   BEGIN

   SCRIPT_FORMAT Verilog_vcd ;

   INPUTS pin1, pin2, pin3, clka, clkb;

   BIDIRECTS iobus[15:0];

   INPUTS ioctrl;

   ORIG_FILE = "filename";

   END

For comparison, if we need to use the full path names option (Verilog_vcd_f), then this might look like:

  OVF_BLOCK

   BEGIN

   SCRIPT_FORMAT Verilog_vcd_f;

   INPUTS top.module1.pin1, top.module1.pin2,

   top.module1.pin3, top.module1.clka,

   top.module1.clkb;

   BIDIRECTS top.module1.iobus[15:0];

   INPUTS top.module1.ioctrl;

   ORIG_FILE = "filename";

   END

Note that in this case, the full hierarchical names must be used throughout the command file. This hierarchy could then be removed in the output file using the global string replacement version of the ALIAS command in the TVF_BLOCK to replace the hierarchy string with NULL:

 ALIAS "top.module." = "";

In the VTRAN® SPICE interface, the INPUTS and BIDIRECTS commands are also used to specify node numbers. A voltage source is created for each stimulus pin by VTRAN. To provide more flexibility in specifying the nodes for this voltage source, specific node numbers can be specified for use instead of nodes names. EVCD, WGL, and STIL files do not require INPUTS/OUTPUTS/BIDIRECTS commands in the OVF_BLOCK. In this case, node references can also be included in the TVF_BLOCK.

The INPUTS, OUTPUTS, and BIDIRECTS commands can be used in any order and as many times as desired to special of the signals you wish to have read from the VCD file.

Analog

For SPICE interfaces, the ANALOG command is available to support the generation of Piecewise Linear continuous analog voltages.

        

   ANALOG busname [,VMAX=value] [,VMIN = value]

Where "busname" is the name of a vectored bus previously defined. The optional parameters VMAX and VMIN specify the voltage range over which the analog signal will vary. If no VMIN or VMAX parameter is specified, then the VIL and VIH values will be used from the SPICE param_list. The number of bits defined for the bus determines the resolution of the analog signal within the voltage range. An example is given below:

   INPUTS pin1 "20", vbus[7:0] "33";

   ANALOG vbus vmin = 0.50, vmax = 5.50;

Here, the 8-bit bus "vbus" is defined as an analog pin, with a voltage range of 5.0 volts (between 0.5 and 5.5). Reading a vbus value of 0 in the OVF would set it to 0.5 volts in the TVF, a value of 'FF' would set it to 5.5 volts and a value of '0F' would set it to 3.0 volts. The voltage translation from digital values to an analog voltage works the same way an A/D converter would.

Like the INPUTS/OUTPUTS/BIDIRECTS command, the ANALOG command can be used as many times as necessary.

Other

The ORIG_FILE command specifies the name of the input vector file. It is not required if the input file name is specified from the command line when invoking VTRAN.

It may be convenient to have VTRAN® extract the pin names from the OVF file for the use of generating pin lists.

        

 VTRAN® -pins verilog_vcd sim.log > pins.log

would place the names of all the pins in the simulation vector file 'sim.log in a file called pins.log

THE PROC_BLOCK

For SPICE Interfaces, the PROC_BLOCK is used to determine the direction of states on bidirectional pins (in the case of VCD files) and specify state mapping.

Bidirectional Pin Control

When a pin or bus is defined as being bidirectional, VTRAN® creates two internal pin versions. One for input and one for output. The input (stimulus) has the defined name and will be used to store the input state data from the OVF. Outputs are not relevant to the SPICE interface. When translating OVF files, VTRAN® must be able to determine when data on a bidirectional pin represents an input state (to be driven) or an output state (expect data) at any given point in time. If the OVF format contains information such that the VTRAN® reader can make this determination, no user commands are required. In the case of VCD files, however, the reader cannot determine pin direction on bidirectional pins because the state information is identical for both driving and sensing cases. BIDIRECT_CONTROL commands in the PROC_BLOCK are available to deal with this requirement.

The BIDIRECT_CONTROL command is used to specify when states represent input data or output data - usually as a logical function of a control signal. An example of this would be:

  BIDIRECT_CONTROL bi1, bi2, bi3, bi4 = INPUT when ctl = 0;

Here we specify that the state data on the bidirectional signals bi1 - bi4 in the VCD file should be interpreted as input data when the control signal ctl is a logic 0. This, by default, implies it is output state data if ctl is not a logic 0 (is a logic 1). The input is assigned a Z state, when the pin direction is determined to be output. All bidirectional signals in the VCD file need to have their data directions specified in a manner similar to this. Multiple BIDIRECT_CONTROL statements can be used (up to one for each bidirectional pin if needed).

State Mapping

The only valid states associated with the PWL statements created by VTRAN® are 0, 1, and Z. These are mapped to voltage levels. See the TVF_BLOCK. All valid input states in the OVF file need to be mapped to 0,1, or Z.

In a standard VCD file, where the state characters are 1,0,X,Z,x, and z, the necessary state mapping can be accomplished with:

  STATE_TRANS inputs 'x'->'0', 'X'->'0', 'z'->'Z' ;

In an EVCD file, the necessary state mapping can be accomplished with:

  STATE_TRANS pure_inputs

   'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1',

   'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'0',

   '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'0',

   'c'->'0', 'f'->'Z', 'F'->'Z';

  STATE_TRANS bidir_inputs

   'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1',

   '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'0',

   'c'->'0';

In a WGL file, the necessary state mapping can be accomplished with:

  STATE_TRANS pure_inputs '-'->'0', 'X'->'0';

  STATE_TRANS bidir_inputs '-'->'Z', 'X'->'0';

In a STIL file, the necessary state mapping can be accomplished with:

  STATE_TRANS pure_inputs

   'D'->'0', 'U'->'1', 'N'->'0', 'L'->'0', 'l'->'0', 'H'->'1',

   'h'->'1', 'X'->'0', 'x'->'0', 'T'->'Z', 't'->'Z',

   '?'->'0', 'N'->'0', 'A'->'0', 'B'->'1'

   'F'->'Z';

  STATE_TRANS bidir_inputs

   'D'->'0', 'U'->'1', 'N'->'0',

   '?'->'0', 'N'->'0', 'A'->'0', 'B'->'1'

   'F'->'Z';

In all of these cases the unknown states are mapped to '0'. These values could also be mapped to '1'. It is the user's choice. The important thing it that all possible states are mapped to 0, 1, or Z. There is no need to provide a '0'=>'0' or a '1'->'1' map.

THE TVF_BLOCK

There are really only two commands required in the TVF_BLOCK of the VTRAN® command file for the generation of a SPICE file. These are the SIMULATOR and INPUTS_ONLY (or INPUTS) command. Other useful commands are RESOLUTION, and TARGET_FILE.

Simulator

The SIMULATOR command specifies the SPICE interface and anyone or all of the SPICE-specific parameters:

 UNITS = units, {defaults to NS}

 TechFile = "filename",

 TRISE = value, {in units specified by "UNITS"; defaults to 1.0 }

 TFALL = value, { in units specified by "UNITS"; defaults to 1.0}

 VIL = value, {in volts; defaults to 0.8}

 VIH = value, {in volts; defaults to 2.0}

 TRIZ = value, {in volts; defaults to 3.4}

 VREF_NODE = node_number ; { defaults to 0 }

Where "units" can be FS, PS, NS, US or MS (applies to parameter list values only); "filename" is the name of the technology file (see description below) containing SPICE related parameters; and "value" can be either MIN, TYP, MAX, or a specific value. When either MIN, TYP or MAX is assigned to a parameter, e.g. TRISE = MAX, the corresponding value for this parameter as listed in the techfile is used. If a specific value is assigned to a parameter (e.g. VIL = 0.25), then this value overrides the value for this parameter in the techfile. Specific values for all parameters can be specified in the param_list, in which case no techfile need be specified. The VREF_NODE parameter is the node number to which all other pins are referenced in the PWL statements. This node defaults to 0 which is normally the ground node.

An example of invoking the SPICE interface with a parameter list would be:

SIMULATOR spice units = NS, Techfile = "fast.tech", trise=typ, tfall=typ, vil=0.15, vih=3.55, triz=2.65;

For each signal transition, VTRAN® creates 2 entries in the PWL statement. For positive going transitions, i.e. 0->1, VTRAN® creates a voltage event that corresponds to the transition event time in the OVF at the lower voltage, i.e. vil. It creates a second voltage event at a time equal to the transition event time plus TRISE at the higher voltage, i.e. vih. Negative going transitions are similarly processed and use TFALL.

Inputs_Only

The INPUTS_ONLY command causes VTRAN® to map only stimulus results. This includes all states on inputs and the input states on bidirectionals. The tristate condition ('Z' state) of bidirectional pins is emulated by a non-0/non-1 (usually midband) voltage level specified by the TRIZ parameter described above. This is not really a high-impedance level. The assumption is that even though this is a bidirectional signal, this voltage is being applied only to the input leg of the circuit.

The INPUTS command can be used instead of the INPUTS_ONLY command to identify and order the pins placed in the TVF file. It can also be used to specify the node number attribute when the OVF is a format that contains pin direction. See "Pin Declaration" in the OVF_BLOCK description. When used with a SPICE interface in the TVF_BLOCK, the INPUTS command should reference all pins with inputs, even bidirectionals. Using a BIDIRECTS command for bidirectional type pins (with a SPICE interface) will incorrectly cause bidirectional output data to be placed in the TVF. Note that VTRAN® will issue a warning when using an INPUTS command with pins previously determined to be bidirectional. This can be safely ignored.

Resolution

The RESOLUTION command affects the processing and output of time stamps. The syntax is:

  RESOLUTION n;

where n is 1.0, 0.1, 0.01, or 0.001.

The time units in the PWL statements are fixed at seconds. By default the RESOLUTION value is 1.0 and specifies a nanosecond (1.00000000000e-09 second value) resolution in the PWL statement. A RESOLUTION value of 0.1 specifies a 0.1 nanosecond (1.00000000000e-10 second value) resolution in the PWL statement. The maximum resolution available in the SPICE interface is picoseconds and is associated with a RESOLUTION value of 0.001.

  IMPORTANT :

  The SIMULATOR parameter list UNITS value does not effect resolution.

Target_File

TARGET_FILE specifies the name of the target vector file.

Example

An example of a TVF_BLOCK for use with a SPICE interface is:

  TVF_BLOCK

   BEGIN

   INPUTS_ONLY;

   SIMULATOR spice units = NS, vil = 1.0, vih = 3.75, triz = 2.0, trise = 4.0, tfall = 4.0;

   TARGET_FILE = "exp1.sp";

   END

THE TECHNOLOGY FILE

The technology file contains MIN and MAX SPICE related parameters. When either MIN, TYP or MAX is assigned to a parameter (e.g. TRISE = MAX), the corresponding value for this parameter as listed in the technology file is used. The TYP value is calculated as the mid-point value between MIN and MAX. The technology file has the following format:

 * MIN MAX UNITS

 trise = 1.00E+00 : 2.00E+00 : ns

 tfall = 1.50E+00 : 2.80E+00 : ns

 VIL = 0.00E+00 : 0.20E+00 : V

 VIH = 2.20E+00 : 2.60E+00 : V

 TRIZ = 1.60E+00 : 1.60E+00 : V

VCD to SPICE EXAMPLE

In this example, a Verilog VCD with a 10ps timescale containing inputs and bidirectional pins is translated into a SPICE data file.

 OVF_BLOCK

  BEGIN

  ORIG_FILE "exp1.vcd";

  SCRIPT_FORMAT verilog_vcd;

  INPUTS C2_LBUSRDY, C1_RSFTEN, C2_CPUACKN ;

  BIDIRECTS L2_LDB31[2:0], L2_LDB30, L2_LDB29, L2_LDB28,

    L2_LDB27, L2_LDB26, L2_LDB25, L2_LDB24, L2_LDB23,

    L2_LDB22, L2_LDB21, L2_LDB20, L2_LDB19, L2_LDB18,

    L2_LDB17, L2_LDB16, L2_LDB15, L2_LDB14, L2_LDB13,

    L2_LDB12, L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8,

    L2_LDB7, L2_LDB6, L2_LDB5, L2_LDB4, L2_LDB3,

    L2_LDB2, L2_LDB1, L2_LDB0 ;

  INPUTS T2_TLBMIS, T2_TLBERR, Y1_CMCPU, YA_ASM,

    YA_TM2, E2_INTREQ2, E2_INTREQ1, E2_INTREQ0,

    U2_ASRTBMK, U2_BRKTYP0, U2_BRKTYP1, Y1_STPCPU,

    YA_HSTBY, E2_RSTAJ, E2_CPURST ;

  BIDIRECTS SA_CPUDMY17, SA_CPUDMY16, SA_CPUDMY15,

    SA_CPUDMY14, SA_CPUDMY13, SA_CPUDMY12, SA_CPUDMY11,

    SA_CPUDMY10, SA_CPUDMY9, SA_CPUDMY8, SA_CPUDMY7,

    SA_CPUDMY6, SA_CPUDMY5, SA_CPUDMY4, SA_CPUDMY3,

    SA_CPUDMY2, SA_CPUDMY1, SA_CPUDMY0 ;

  OUTPUTS EMWHHP, EMWBHP, EMWLHP, EMWBLP ;

  END;

 PROC_BLOCK

  BEGIN

  STATE_TRANS inputs 'x'->'0', 'X'->'0', 'z'->'Z' ;

  BIDIRECT_CONTROL L2_LDB31, L2_LDB30, L2_LDB29,

    L2_LDB28, L2_LDB27, L2_LDB26, L2_LDB25, L2_LDB24,

    L2_LDB23, L2_LDB22, L2_LDB21, L2_LDB20, L2_LDB19,

    L2_LDB18, L2_LDB17, L2_LDB16 = output when EMWHHP = 1;

  BIDIRECT_CONTROL L2_LDB15, L2_LDB14, L2_LDB13, L2_LDB12,

    L2_LDB11, L2_LDB10, L2_LDB9, L2_LDB8 = output when EMWBHP | EMWLHP = 1;

  BIDIRECT_CONTROL L2_LDB7 L2_LDB6 L2_LDB5 L2_LDB4 L2_LDB3

    L2_LDB2 L2_LDB1 L2_LDB0 = output when EMWBLP = 1;

  END;

 TVF_BLOCK

  BEGIN

  INPUTS_ONLY;

  SIMULATOR spice

    units = NS,

    vil = 1.0,

    vih = 3.75,

    triz = 2.0,

    trise = 0.04,

    tfall = 0.04;

  RESOLUTION 0.01;

  TARGET_FILE = "exp1.sp";

  END; 

EVCD to SPICE EXAMPLE

In this example, a similar Verilog EVCD file is translated into a SPICE data file.

 OVF_BLOCK

  BEGIN

  ORIG_FILE "exp1.evcd";

  SCRIPT_FORMAT verilog_vcd;

  END;

 PROC_BLOCK

  BEGIN

 STATE_TRANS pure_inputs

   'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1',

   'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'0',

   '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'0',

   'c'->'0', 'f'->'Z', 'F'->'Z';

 STATE_TRANS bidir_inputs

   'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1',

   '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'0',

   'c'->'0';

  END;

 TVF_BLOCK

  BEGIN

  INPUTS_ONLY;

  SIMULATOR spice

    units = NS,

    vil = 1.0,

    vih = 3.75,

    triz = 2.0,

    trise = 0.04,

    tfall = 0.04;

  RESOLUTION 0.01;

  TARGET_FILE = "exp2.sp";

  END; 

STIL to SPICE EXAMPLE

In this example, a STIL file is translated into a SPICE data file. The default resolution of 1 nanosecond is used. Notice how closely this resembles the EVCD to SPICE example. The only significant different is the STATE_TRANS command in the PROC_BLOCK .

 OVF_BLOCK

  BEGIN

  ORIG_FILE = "exp3.stil";

  TABULAR_FORMAT stil;

  END;

 PROC_BLOCK

  BEGIN

  STATE_TRANS pure_inputs

   'D'->'0', 'U'->'1', 'N'->'0', 'L'->'0', 'l'->'0', 'H'->'1',

   'h'->'1', 'X'->'0', 'x'->'0', 'T'->'Z', 't'->'Z',

   '?'->'0', 'N'->'0', 'A'->'0', 'B'->'1'

   'F'->'Z';

 STATE_TRANS bidir_inputs

   'D'->'0', 'U'->'1', 'N'->'0',

   '?'->'0', 'N'->'0', 'A'->'0', 'B'->'1'

   'F'->'Z';

  END;

 TVF_BLOCK

  BEGIN

  INPUTS_ONLY;

  SIMULATOR spice

    units = NS,

    vil = 1.0,

    vih = 3.75,

    triz = 2.0,

    trise = 4.0,

    tfall = 4.0;

  TARGET_FILE = "exp3.sp";

  END;  

WGL to SPICE EXAMPLE

In this example, a WGL file is translated into a SPICE data file. It uses the Technology File and MIN references to specify vil, vih, triz, trise, tfall. It uses the TVF_BLOCK INPUTS command to specify node numbers.

If some of the signals in the input (WGL) file are bidirects, note that we want to define them as INPUTS in the TVF_BLOCK so that only the input side of the bidirects are translated. In tis case warnings like:

  *** Warning - Pin 'bidirNrzSig' in the TVF has had its direction redefined.

   This may cause translation problems.

  *** Warning - Pin 'bidirRzSig' in the TVF has had its direction redefined.

   This may cause translation problems.

  *** Warning - Pin 'bidirRoSig' in the TVF has had its direction redefined.

   This may cause translation problems.



can be ignored.



 OVF_BLOCK

  BEGIN

  ORIG_FILE = "exp4.wgl";

  TABULAR_FORMAT wgl;

  END;

 PROC_BLOCK

  BEGIN

  STATE_TRANS pure_inputs '-'->'0', 'X'->'0';

  STATE_TRANS bidir_inputs '-'->'Z', 'X'->'0';

  END;

 TVF_BLOCK

  BEGIN

  SIMULATOR spice

    techfile= "exp4.tech",

    vil = MIN,

    vih = MIN,

    triz = MIN,

    trise = MIN;

  INPUTS nrzSig1 "0", nrzSig2 "1", nrzSig3 "2", nrzSig4 "4", OE "3" ;

  INPUTS bidirNrzSig "5", bidirRzSig "6", bidirRoSig "7";

  INPUTS CLOCK "9";

  TARGET_FILE = "exp4.sp";

  END; 

Product Support

Customer Quotes

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  • We currently use VTRAN for translating WGL, EVCD and VCD vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
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