Simulate Translate Test

Control Signal and Vector Insertion for Q-Star Test Modules

This Application Note describes how to use VTRAN® to automatically insert control signals and control vectors into WGL or STIL files which have been generated specifically for IDDQ current testing. The modifications to the vectors made by VTRAN® provide support for Q-Star Test's family of advanced, high-speed IDDQ/ISSQ test and measurement modules. These Ixxx modules have the unique characteristic of being virtually transparent to the device under test and to the automatic test equipment (ATE). The specific Q-Star module types currently supported are the QD-10xx product family in general and the QD-1011, QD-1011HC24 and QD-1011HCLite more specifically.

These products are typically placed on the interface board (loadboard, probe card, dut board, ...) that connects the device under test with the ATE system. Q-Star has developed it's products so that they are test system independent and can be used on any test platform. The concept of the modules is that for the ATE system they look like part of the DUT and for the DUT they look like they are part of the ATE. The only penalty for this is that required control and communication has to be embedded in the test program, and this is place where VTRAN® fits in. Using VTRAN's ability to automatically insert control signals and vectors into the ATPG vectors, the Q-Star Ixxx test modules become very easy to use and it becomes very easy to exploit their full capabilities, making high-speed and high accuracy current measurements very accessible.

Overview

A number of automatic test program generation (ATPG) products today provide options for generating a set of vector data that will setup the device for a current measurement, usually IDDQ. Based upon simulations and empirical data, these measurements can provide a very good indicator as to whether or not the device is functioning correctly. A fast, highly accurate current measuring device can thus greatly improve the average test time as well as the reliability for complex ICs.

Within the WGL or STIL files that are generated for IDDQ testing, there are normally markers located at points in the vector sequences where the current test should take place. For WGL files, this marker is usually an annotation which is something like { measureIDDQ }. In the STIL syntax there is a specific statement available for this: IddqTestPoint; . In order to activate and control the Q-Star IDDQ test module, VTRAN® makes the following modifications to the WGL or STIL vectors:

  • Add 3 signals to the vector data which are used to communicate with the test module. Two of the signals are inputs; MD is a data input, CLK is a communication synchronization input. The third signal, DOUT, is an output. VTRAN® adds these 3 signals to the WGL/STIL file, plus sets default timing for them, during the read process.
  • Insert some optional initialization vectors at the beginning of the pattern set. The measurement modules have default settings, but if test conditions or protocols are desired that are different than the defaults, then these initialization vectors need be inserted. Typically, these vectors would be used to configure the module for operating mode, sample setting and global reference setting when appropriate.
  • At each location in the pattern file where an IDDQ marker is found, VTRAN® will insert the appropriate vector sequence depending the options selected by the user.
  • At the end of the pattern vectors, VTRAN® will insert some vectors to read out stored measurement data from the module if the appropriate option is set by the user.

For all vectors that are inserted by VTRAN®, only the 3 added signals are used. For all other signals, the outputs are set to X (don't care), non-clock inputs maintain their last state, and clock signals are disabled.

INSERTING CONTROL SIGNALS AND VECTORS

The insertion of control signals and vectors by VTRAN® happens during the reading of the WGL or STIL files by the respective canned reader. It is therefore independent of the target output format. This means that the insertions can be performed during translations from WGL/STIL to any of the test (ATE) formats VTRAN® supports, or back to another WGL or STIL file. Instructing VTRAN® to perform the Q-Star flow insertions is accomplished using a Q-Star statement block that is added to the OVF_BLOCK of the VTRAN® command file. This Q-Star statement block has the following syntax and parameter:

options ([ ] means optional parameter):



    Q-Star

    Product = "QD1011 | QD1011HC24 | QD1011HCLite",

    [Keyword = "IDDQ_keyword",] { default is measureIDDQ }

    [Comtest = "Y | N",]

    [SF = "Y | N"],

    [Mode = "1 | 2",]

    [Sample = "1 | 4 | 16 | 256 | 1024",]

    [GRef = "N|S|D, value_1, [value_2]",]

    [VRef = "N|Y, [vec#, value_1 [,vec#, value_2]]",]

    [NoM = "N|Y, value",]

    [Readout = "N|A|S, [SV|DV,] [1,2,...N]",]

    [MemRead = "N|Y, [value]"]

    ;

These parameters have the following meanings:

Product: Used to identify the Q-Star IDDQ test module type being used

Keyword: Used when the input file is WGL to indicate the annotation text string which identifies the IDDQ test points in the vector data. The default for this is "measureIDDQ".

ComTest : is used to specify whether or not a communication test is to be done at the start of the test program.

SF: is used to specify whether or not a special function is to be executed at the start of the test program.

Mode: is used to specify the desired measurement operating mode (1 or 2))

Sample: is used to specify the number of samples taken on which a measurement result will be based

GRef: is used to specify if global pass/fail references will be used

VRef: is used to specify if vector specific reference values are to be used and prior to which measurement the vector specific reference value specified is to be inserted (pass/fail references set remain valid till a new value is shifted into the module)

NoM: is valid when the module supports pre/post stress delta-IDDQ and is used to specify the number of pre and post stress measurements

Readout: If the first parameter associated with Readout is "N" or "A" then no other parameters must be specified. The range specifier "-" is not allowed when specifying the readout points, only a enumerated list is supported.

MemRead: is used to specify how many values need to be read back from the module at the end of the pattern data.

For each of the specific Products (test module types), the combination of valid parameters will depend on the specific test and protocol objectives. Refer to the literature and technical assistance provided by Q-Star Test ( www.QStar.be ) for detailed information on these.

THE OVF_BLOCK OF VTRAN® COMMAND FILE

Included in the VTRAN® software bundles that are available from our web site is a QStar directory which contains information on the vectors to be inserted as a result of the different parameters. In order to tell VTRAN® to perform the insertions, a Q-Star statement block is inserted in the OVF_BLOCK which specifies the various parameter values for the desired current testing. When using this Q-Star insertion flow, the WGL and STIL readers should be invoked as follows ([ ] indicates optional):

tabular_format wgl -cycle -scan -keep_annotations

    [-include_cells] [-expand_reps] ;

or

tabular_format stil -cycle -scan [-keep_annotations]

    [include_cells] [-expand_reps] ;

For both readers, the -include_cells flag is only necessary if the output format is either WGL or STIL also (i.e. going from WGL/STIL -> WGL/STIL). For ATE test pattern output, this flag should not be used. The vectors that get inserted by VTRAN® into the Q-Star Test flow typically contain a large number of repeat vectors which by default will become repeat vectors in the target output file also. If this is not desirable, or if the target test system does not support repeat vectors, then the -expand_reps flag can be used to tell VTRAN® to expand the repeats into multiple single vectors. Following are some examples of command file OVF_BLOCKs:

EXMAPLE 1:



OVF_BLOCK

  begin

  orig_file = "Design1.wgl";

  tabular_format WGL -cycle -scan -keep_annotations -include_cells ;

  Q-Star

    Product = "QD1011",

    Keyword = "measIDDQ",

    ComTest = "Y",

    Sample = "1",

    GRef = "D 0.4mA 0.8mA",

    Mode = "1"

    ;

  end



EXAMPLE 2:



OVF_BLOCK

  begin

  orig_file = "Design2.stil";

  tabular_format STIL -cycle -scan -keep_annotations ;

  Q-Star

    Product = "QD1011HC24",

    ComTest = "Y",  Sample = "4",

    GRef = "D 9A 18A",

    Mode = "2",

    MemRead = "Y 5"

    ;

  end

THE PROC_BLOCK and TVF_BLOCK

The only part of a VTRAN® command file which is affected by the Q-Star control insertion is the OVF_BLOCK as described above. The PROC_BLOCK and TVF_BLOCK of the command file will remain exactly the same as they would be if the insertions were not taking place. For information on the contents of these blocks in the command file, refer to the other Application Notes for WGL or STIL translations. For example translations using this flow, also see the INTERFACES directory bundle (INTERFACES/QSTAR) available on the Source III web site at: www.sourceiii.com/downloads.html.

Product Support

Customer Quotes

  • Intrinsix Uses VTRAN® to Speed Vector Translation Flow "I had one customer who used VHDL for RTL, Verilog for gate level simulation, and sometimes used EPIC tools. Getting vectors into the various formats was a nightmare. VTRAN® made the translation process easy and seamless. Plus, WGL or STIL for the test group. Support from Source III has also been quite impressive. In one case, they wrote a bug fix for me in under a day." John Weiland Intrinsix Consultant  
  • We use VTRAN® to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly.
  • Sanera Utilizes Full Featured VTRAN® to Convert Functional and ATPG Vectors "We chose VTRAN® because it can handle multiple simulation file formats (including VCD and WGL) from a single tool. VTRAN's commands are easy to use. The flexibility in pin mapping, masking outputs, and generating scan-based vectors proves to be tremendously helpful. And most of all, Source III provides excellent, fast response to our support needs. This helps us to get things moving very quickly - making good solid progress." Ken ChenTest Engineering Manager
  • VTRAN® is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with Source III has been positive and their support is extremely responsive and timely.
  • Source III VTRAN® tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion
  • We currently use VTRAN for translating WGL, EVCD and VCD vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
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