Simulate Translate Test

MultiTimeDomain Test Programs

Using VTRAN® to Create MultiTimeDomain Test Programs

VTRAN® can be used to create functional test programs with multiple time domains. This is generally a requirement of System on a chip (SoC) designs. For target tester hardware that supports the simultaneous execution of pattern bursts with different tester cycle lengths, VTRAN's reader capability can be used to extract waveform data from the vector source on a per time domain basis. VTRAN's tester interfaces can then translate this data into a set of functional test programs for parallel loading and execution on the tester. When concurrent execution of test programs with different periods is not supported in tester hardware, however, VTRAN® can still be used to generate functional test programs in many useful cases. This Application Note provides complete examples of the entire translation process, but focuses mainly on the commands and features related to multiple time domains. Some background on the cyclization features of VTRAN® is helpful and the reader is encouraged to review the information provided in the Application Notes titled "VTRAN® Template Cyclization Feature" and "Print-on-change to Cycle-based Translations" available in the Appilcation Notes. See the VTRAN® Users Guide for a complete reference of the existing features.

OVERVIEW

The VTRAN® translation process is divided into three separate tasks that correspond to the three blocks in the VTRAN® command file - the OVF_BLOCK, the PROC_BLOCK, and the TVF_BLOCK. The OVF_BLOCK is used to tell VTRAN® how to read the Original Vector File (OVF). VTRAN's reader technology enables it to read almost any simulation or ATPG-generated data file. VTRAN® includes canned readers for print-on-change formats including Verilog VCD/EVCD, cyclized formats including STIL, WGL as well as support for user formats. Commands in the OVF_BLOCK allow the user to select only those signals of interest. The PROC_BLOCK contains commands that tell VTRAN® what data processing functions you want performed during translation. Types of processing include bidirectional data control, state mapping, and cyclization. Finally, the TVF_BLOCK contains commands that specify the desired output format.

Three multidomain cases are described in this application note. They are:

  • Case 1: The Alternate Clock Domains are Integer Multiples of the Fast Clock
  • Case 2: The Least Common Multiple Cycle Length Across Clock Domains is a "Reasonable" Value
  • Case 3: Asynchronous Clock Domains

Case 1

The Alternate Clock Domains are Integer Multiples of the Fast Clock

As suggested by the title, in this case each clock domain is an integer multiple of the fastest clock. An example is shown in Figure 1.

In this example, domain2_CLOCK (60ns period) runs at one third the frequency of domain1_CLOCK (20ns period). Equivalently, the cycle length associated with signals in domain2 is three times the cycle length of the signals of domain1. Notice that despite the difference in frequency, all these waveforms can be generated on a target tester that does not support multiple time domains by cyclizing all signals using the period of the faster clock in domain1. The cyclization strategy on the base time domain (Domain1) is unaffected by this choice, but for the signals in Domain2 this is not the case. For example, when cyclized on a 60ns cycle, the format associated with the slower clock in Domain2 is RZ, but when cyclized on the 20ns cycle, the format is NRZ. See also, that the output signals associated with the slower clock domain must be masked on 2 out of every 3 of the 20ns subcycles.

Once the timing analysis is complete, Approach 1: ALIGN_TO_CYCLE, CYCLE, PINTYPE outlined in the " Print-on-change to Cycle-based Translations" Application note can be used to control the cyclization process.

For output signals, it is typically desirable to sample the output states for each cycle somewhere towards the end of the cycle. The outputs for Domain1 can be setup for sampling in every cycle, since the cyclization is using the cycle time (20ns) for this domain. However, the output signals for Domain2 should only be sampled at the end of every third cycle since this domain has a 60ns period. Essentially, we need to mask the outputs for Domain2 during the first 2 (of each 3) cycles. This strobe management can be handled using the VTRAN® ADD_PIN and MASK_PIN statements. First, ADD_PIN is used to create a "mask control signal" with a constant state assignment. Then the SEQUENCE form of the MASK_PINS command is used to create a pattern of states on the "mask control signal" that indicates in which cycles we want mask the Domain2 outputs. Finally, the CONDITION form of the MASK_PINS command is used with this "mask control signal" to mask the strobe state generated during the cyclization process for all but the desired (every third) cycles.

  ADD_PIN MASK_CTRL = 1;  {creates MASK_CTRL with constant state 1}
  MASK_PINS MASK_CTRL @SEQUENCE "111", "110";  {assigns "mask" pattern}
  MASK_PINS domain2_outSig1 @CONDITION MASK_CTRL = 1;  {forces don't
     care's on masked cycles}

During test program generation, the mask control signals are removed from the target test program using the DELETE_PINS command in the TVF_BLOCK.

DELETE_PINS MASK_CTRL = 1;

The following VTRAN® command file translates a standard Verilog EVCD file with the waveform shapes illustrated in Figure 1 to an Advantest T3300 test program.

OVF_BLOCK
 BEGIN
 SCRIPT_FORMAT Verilog_vcd ;
 ORIG_FILE = "exp2.evcd";
 END
PROC_BLOCK
 BEGIN
 ADD_PIN MASK_CTRL =1;
 MASK_PINS MASK_CTRL @ SEQUENCE "111", "110";
 MASK_PINS MASK_CHARACTER = 'X' domain2_outSig1, domain2_outSig2
   @ CONDITION MASK_CTRL = 1;
 ALIGN_TO_CYCLE 20 domain1_CLOCK @10, domain1_nrzSig1 @5,
   domain1_outSig1 @17,
   domain2_CLOCK @18, domain2_nrzSig1 @5, domain2_outSig1 @10,
   domain2_outSig2 @15;
   
 CYCLE 20;
 PINTYPE rz domain1_CLOCK @ 5, 15;
 PINTYPE nrz domain1_nrzSig1 @ 0;
 PINTYPE stb domain1_outSig1 @ 16;
 PINTYPE nrz domain2_CLOCK @ 15;
 PINTYPE nrz domain2_nrzSig1 @ 0;
 PINTYPE stb domain2_outSig1 @ 13;
 PINTYPE stb domain2_outSig2 @ 17;
 STATE_TRANS pure_inputs
  'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1',
  'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'0', 'x'->'0',
  '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'0',
  'c'->'0', 'f'->'0', 'F'->'0';
 STATE_TRANS pure_outputs
  'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X',
  'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X',
  '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
  'c'->'H', 'f'->'Z', 'F'->'X';
 STATE_TRANS bidir_inputs
  'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1',
  '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X',
  'c'->'X';
 STATE_TRANS bidir_outputs
  'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X',
  '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
  'c'->'H', 'f'->'Z', 'F'->'X';
 END
TVF_BLOCK
 BEGIN
 DELETE_PINS MASK_CTRL;
 tester_format Advantest -T3300,
  TIME_STAMPS = "ON";
 target_file = "adv1";
 END

In the example, the rising and falling edges of the slower clock occur at the same time relative to the base period. If this is not the case, and if the target tester supports different time offsets for transition to logic 1 and transition to logic 0, an NRZ2 format can be specified in the PINTYPE statement.

PINTYPE nrz2 domain2_CLOCK @ 15, 10;

Alternatively, multiple timesets can be created using VTRAN's TEMPLATE_CYCLIZATION feature.

Important note about the use of the SEQUENCE form of MASK_PINS.

When constructing the pattern state sequence for use in identifying active strobe/masked strobe subcycles, it is important to understand how the SEQUENCE form of MASK_PINS is implemented. The check for a sequence replacement is done at every vector position. This happens regardless of whether or not the current vector position is from the original stream or is the result of a previous replacement. For example:

ADD_PIN MASK_CTRL = 1;
     MASK_PINS MASK_CTRL @SEQUENCE "1111", "0111";

results in a pattern state sequence of mostly 0's. In order to generate the sequence "0111011101110111..." use:

  ADD_PIN CTL = 0;
  MASK_PINS CTL @ SEQUENCE "0000" "0111";

An alternative to this would be to use the SEQUENCE_BLOCK option which would give the same pattern for either of these appraoches. See the "Masking Pins in Target Vector File using MASK_PINS" Application Note for more information on using the MASK_PINS command.

Case 2

The Least Common Multiple Cycle Length Across
Clock Domains is a "Reasonable" Value

This situation occurs when the Least Common Multiple (LCM) of the period values across all time is of "reasonable" length. For example, if one clock domain (Domain1) is based on a 30ns period and a second clock domain (Domain2) is based on a 40ns period, the overall period value is 120ns. The relationship between the clock domains is the same over 120ns intervals. This happens as a result of the fact that both 30 and 40 divide evenly into 120. See Figure 3.

The relationship between the clock domains is also maintained over 240ns and 360ns periods, but the smallest period for which this is true is the Least Common Multiple (LCM) of 30ns and 40ns, which is 120ns. A set of test program cycles that "tile" this LCM period can be used to generate waveforms across all the time domains.

Example: Choosing a Test Program Cycle with Length Equal to the Fastest Clock

In this example, a 30ns test program cycle has been chosen. It divides evenly into the LCM period of 120ns. Using the waveforms shown above, see that this potentially results in generation of up to four timesets as 30ns divides into 120ns four times. The Domain1 timing for each timeset will remain constant, while that for the Domain2 signals may vary between each timeset. See Figure 4.

The following VTRAN® command file, cyclizes the waveforms shown above using 30ns as the test program cycle. It uses VTRAN's TEMPLATE CYCLIZATION feature to generate multiple timesets. In this case, the strobes in the second domain are active in three out of every four subcycles.

 OVF_BLOCK
   BEGIN
   ORIG_FILE "exp2.evcd";
   SCRIPT_FORMAT verilog_vcd;
   END
 PROC_BLOCK
   BEGIN
   ADD_PIN MASK_CTRL = 0;
   MASK_PINS MASK_CTRL @SEQUENCE "0000", "0111";
   MASK_PINS domain2_outSig1 @CONDITION MASK_CTRL = 0;
   TEMPLATE_CYCLIZATION
    TERMINATE_ON_DEFAULTS = "1", {# stop on no match}
    MATCH_REPORT = "match.rpt",
    MATCH_TRACE_START = 1, {# detail trace parameters }
    MATCH_TRACE_STOP = 20;
    TIMESET T1
     CYCLE 30;
     PINTYPE rz domain1_CLOCK @ 10, 20;
     PINTYPE nrz domain1_nrzSig1 @ 0;
     PINTYPE stb domain1_outSig1 @ 16;
     SAMPLE_POINT domain2_CLOCK @ 20;
     IDENTIFIER domain2_CLOCK = U; {# match criteria}
     PINTYPE nrz domain2_CLOCK @ 15;
     PINTYPE nrz domain2_nrzSig1 @ 0;
    ENDTIMESET;
    TIMESET T2
     CYCLE 30;
     WEIGHT 1; {# match weight - choose T2 when T2 and T3 matches }
     PINTYPE rz domain1_CLOCK @ 10, 20;
     PINTYPE nrz domain1_nrzSig1 @ 0;
     PINTYPE stb domain1_outSig1 @ 16;
     PINTYPE -PRIMARY -ACTIVE_ONLY RO domain2_CLOCK @ 5,25 ;
                  {# match criteria/sample directive/test spec }
     PINTYPE nrz domain2_nrzSig1 @ 0;
     PINTYPE stb domain2_outSig1 @ 3;
    ENDTIMESET;
    TIMESET T3
     CYCLE 30;
     PINTYPE rz domain1_CLOCK @ 10, 20;
     PINTYPE nrz domain1_nrzSig1 @ 0;
     PINTYPE stb domain1_outSig1 @ 16;
     SAMPLE_POINT domain2_CLOCK @ 20;
     IDENTIFIER domain2_CLOCK = D; {# match criteria}
     PINTYPE nrz domain2_CLOCK @ 15;
     PINTYPE nrz domain2_nrzSig1 @ 0;
     PINTYPE stb domain2_outSig1 @ 13;
    ENDTIMESET;
    TIMESET T4
     CYCLE 30;
     WEIGHT 1; {# match weight - choose T4 when T1 and T4 matches }
     PINTYPE rz domain1_CLOCK @ 10, 20;
     PINTYPE nrz domain1_nrzSig1 @ 0;
     PINTYPE stb domain1_outSig1 @ 16;
     PINTYPE -PRIMARY -ACTIVE_ONLY RZ domain2_CLOCK @ 5,25;
                  {# match criteria/sample directive/test spec }
     PINTYPE nrz domain2_nrzSig1 @ 0;
     PINTYPE stb domain2_outSig1 @ 23;
    ENDTIMESET;
   STATE_TRANS pure_inputs
    'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1',
    'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'0', 'x'->'0',
    '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'0',
    'c'->'0', 'f'->'0', 'F'->'0';
   STATE_TRANS pure_outputs
    'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X',
    'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X',
    '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
    'c'->'H', 'f'->'M', 'F'->'X';
   STATE_TRANS bidir_inputs
    'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1',
    '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X',
    'c'->'X';
   STATE_TRANS bidir_outputs
    'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X',
    '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
    'c'->'H', 'f'->'M', 'F'->'X';
   END
 TVF_BLOCK
   BEGIN
   DELETE_PINS MASK_CTRL;
   TESTER_FORMAT teradyne -FLEX+
   WR_TIMESET_FILE="exp2";
   TARGET_FILE="exp2.flex";
   END

The match report (match.rpt) shows that the timesets have been applied as desired during the translation.

   CYCLE-MATCHING SCORE TRACE
   --------------------------

   SCORE: 0 = MISMATCH
          1 = PASSIVE MATCH
          2 = ACTIVE MATCH
        > 2 = ACTIVE MATCH + WEIGHT

   TIMESET COLUMNS:
    A = T1
    B = T2
    C = T3
    D = T4

            A     B     C     D     MATCH
   CYCLE# SCORE SCORE SCORE SCORE (DEFAULT) Time
     1       2     0     0     0     A     0.000
     2       0     3     2     0     B     30.000
     3       0     0     2     0     C     60.000
     4       2     0     0     3     D     90.000
     5       2     0     0     0     A     120.000
     6       0     3     2     0     B     150.000
     7       0     0     2     0     C     180.000
     8       2     0     0     3     D     210.000
    .
    .
    .

Notice that in this case, timesets T1 and T3 can be collapsed into a single timeset. The following TEMPLATE CYCLIZATION commands can be used. There is no need to alter the strobe management statements.

TEMPLATE_CYCLIZATION
   TERMINATE_ON_DEFAULTS = "-1", {# don't terminate when default used }
    MATCH_REPORT = "match.rpt",
    MATCH_TRACE_START = 1, {# detail trace parameters }
    MATCH_TRACE_STOP = 8;
    TIMESET T1_T3 -DEFAULT {# default timeset}
     CYCLE 30;
     PINTYPE rz domain1_CLOCK @ 10, 20;
     PINTYPE nrz domain1_nrzSig1 @ 0;
     PINTYPE stb domain1_outSig1 @ 16;
     PINTYPE nrz domain2_CLOCK @ 15;
     PINTYPE nrz domain2_nrzSig1 @ 0;
     PINTYPE stb domain2_outSig1 @ 13;
    ENDTIMESET;
    TIMESET T2
     CYCLE 30;
     PINTYPE rz domain1_CLOCK @ 10, 20;
     PINTYPE nrz domain1_nrzSig1 @ 0;
     PINTYPE stb domain1_outSig1 @ 16;
     PINTYPE -PRIMARY -ACTIVE_ONLY RO domain2_CLOCK @ 5,25 ;
          {# match criteria/sample directive/test spec }
     PINTYPE nrz domain2_nrzSig1 @ 0;
     PINTYPE stb domain2_outSig1 @ 3;
    ENDTIMESET;
    TIMESET T4
     CYCLE 30;
     PINTYPE rz domain1_CLOCK @ 10, 20;
     PINTYPE nrz domain1_nrzSig1 @ 0;
     PINTYPE stb domain1_outSig1 @ 16;
     PINTYPE -PRIMARY -ACTIVE_ONLY RZ domain2_CLOCK @ 5,25;
          {# match criteria/sample directive/test spec }
     PINTYPE nrz domain2_nrzSig1 @ 0;
     PINTYPE stb domain2_outSig1 @ 23;
    ENDTIMESET;

Example: Using "Small" Test Program Cycle Lengths

For some testers, the tester hardware does not allow for changing the "format on the fly" as required in the example above. See that T1->T2->T3->T4 requires the format on domain2_CLOCK to sequence NRZ->RO->NRZ->RZ. As a result, it may be necessary to determine a tester cycle length that does not imply format changes in the pattern burst. In this example, a 10ns period does the job providing that 10ns periods are supported on the target tester hardware. It divides evenly into the LCM of the clock periods and no tester cycle requires more than one edge on any pin. This means all input signals can be assigned an NRZ format. Notice that now the situation is very similar to that shown in Case 1, except that the strobe management will now have to be applied to all output signals.

Here an example of the VTRAN® command used in this translation.

 OVF_BLOCK
   BEGIN
   ORIG_FILE "exp2.evcd";
   SCRIPT_FORMAT verilog_vcd;
   END
 PROC_BLOCK
   BEGIN
   ADD_PIN MASK_CTRL1 = 0;
   ADD_PIN MASK_CTRL2 = 0;
   MASK_PINS MASK_CTRL1 @SEQUENCE "000", "001";
   MASK_PINS MASK_CTRL2 @SEQUENCE "0000", "0001";
   MASK_PINS domain1_outSig1 @CONDITION MASK_CTRL1 = 0;
   MASK_PINS domain2_outSig1 @CONDITION MASK_CTRL2 = 0;
   ALIGN_TO_CYCLE 10 domain1_CLOCK @5, domain1_nrzSig1 @5,
       domain1_outSig1 @7,
       domain2_CLOCK @5, domain2_nrzSig1 @5, domain2_outSig1 @3;
   CYCLE 10;
   PINTYPE nrz domain1_CLOCK @ 0;
   PINTYPE nrz domain1_nrzSig1 @ 0;
   PINTYPE stb domain1_outSig1 @ 6;
   PINTYPE nrz domain2_CLOCK @ 5;
   PINTYPE nrz domain2_nrzSig1 @ 0;
   PINTYPE stb domain2_outSig1 @ 3;
   STATE_TRANS pure_inputs
    'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1',
    'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'0', 'x'->'0',
    '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'0',
    'c'->'0', 'f'->'0', 'F'->'0';
   STATE_TRANS pure_outputs
    'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X',
    'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X',
    '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
    'c'->'H', 'f'->'M', 'F'->'X';
   STATE_TRANS bidir_inputs
    'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1',
    '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X',
    'c'->'X';
   STATE_TRANS bidir_outputs
    'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'M', 'x'->'X',
    '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
    'c'->'H', 'f'->'M', 'F'->'X';
 TVF_BLOCK
   BEGIN
   DELETE_PINS MASK_CTRL1, MASK_CTRL2;
   TESTER_FORMAT teradyne -FLEX+
   WR_TIMESET_FILE="exp2";
   TARGET_FILE="exp2.flex";
   END

It is necessary to consider the impact on format and timeset assignments when choosing test program period values. The choice of tester cycle length involves the analysis of shape versus size and consideration of the the total number of unique timesets needed to completely generate the desired waveform. Generally, the smaller the period, the less complicated the shape or format, but of course the number of target tester vectors generated increases with smaller period times. Conversely, larger period values correlate to more complicated shape and format assignments. When the tester cycle length is a divisor of the the lease common multiple of periods across all waveforms, the maximum number of required unique timesets is this divided by the tester cycle length. The actual value is often less, as shown in the above examples. The optimal choice will be dictated by the target tester capabilities in regards to minimum cycle lengths, format selection, amount of vector memory, number of timesets, and format/timeset switch capabilities.

Case 3

Asynchronous Clock Domains

When clock domains are asynchronous, there is no reasonable set of tester cycles that can be used to "tile" the LCM period value. For example, it may be that one clock domain is based on a 10ns value while a second clock domain is based on a 6.766 ns value. Generally in this situation, the target tester hardware must support the simultaneous execution of multiple tester cycle lengths. VTRAN® supports the generation of multidomain test programs via multiple passes with one pass per timing domain.

Example: Generating a MultiTime Domain Test Program on the Verigy 93000

The multiport feature gives the Verigy 93000 the ability to simultaneously execute independent time domains. In the following example, a Verilog EVCD file containing two clock domains is translated by VTRAN® into a multidomain test program in two passes. The first pass is for all signals synchronous with the first clock and the second pass is for signals synchronous to the second clock.

 OVF_BLOCK
  BEGIN
  SCRIPT_FORMAT Verilog_vcd ;
  ORIG_FILE = "exp2.evcd";
  { extract domain1 signals from source }
  INPUTS domain1_CLOCK, domain1_nrzSig1;
  OUTPUTS domain1_outSig1;
  END
  PROC_BLOCK
  BEGIN
  { cyclize domain1 signals }
  ALIGN_TO_CYCLE 10 domain1_CLOCK @5, domain1_nrzSig1 @2,
   domain1_outSig1 @8;
  CYCLE 10;
  PINTYPE rz domain1_CLOCK @ 2, 5;
  PINTYPE nrz domain1_nrzSig1 @ 0;
  PINTYPE stb domain1_outSig1 @ 8;
  { state character translations for 'EVCD'->'Verigy 93K'}
  STATE_TRANS pure_inputs
   'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1',
   'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'0',
   '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'0',
   'c'->'0', 'f'->'Z', 'F'->'Z';
  STATE_TRANS pure_outputs
   'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X',
   'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X',
   '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
   'c'->'H', 'f'->'Z', 'F'->'X';
  STATE_TRANS bidir_inputs
   'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1',
   '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X',
   'c'->'X';
  STATE_TRANS bidir_outputs
   'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X',
   '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
   'c'->'H', 'f'->'Z', 'F'->'X';
  END
  TVF_BLOCK
  BEGIN
  TARGET_FILE = "expd1.avc";
  TESTER_FORMAT hp93000
   -auto_group,
   TIME_STAMPS = "ON",
   PIN_CONFIG_FILE = "expd1.pins",
   DVC_FILE = "expd1.dvc";
  RESOLUTION 0.001;
  END

          -------------------------------------------------------------

 OVF_BLOCK
  BEGIN
  SCRIPT_FORMAT Verilog_vcd ;
  ORIG_FILE = "exp2.evcd";
  { extract domain2 signals from source }
  INPUTS domain2_CLOCK, domain2_nrzSig1;
  OUTPUTS domain2_outSig1;
  END
  PROC_BLOCK
  BEGIN
  { cyclize domain2 signals }
  ALIGN_TO_CYCLE 6.766 domain2_CLOCK @3, domain2_nrzSig1 @2,
   domain2_outSig1 @5;
  CYCLE 6.766;
  PINTYPE rz domain2_CLOCK @ 1, 4;
  PINTYPE nrz domain2_nrzSig1 @ 0;
  PINTYPE stb domain2_outSig1 @ 5;
  { state character translations for 'EVCD'->'Verigy 93K'}
  STATE_TRANS pure_inputs
   'D'->'0', 'U'->'1', 'n'->'0', 'N'->'0', 'd'->'0', 'u'->'1',
   'L'->'0', 'H'->'1', 'l'->'0', 'h'->'1', 'T'->'Z', 'x'->'0',
   '?'->'0', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'0',
   'c'->'0', 'f'->'Z', 'F'->'Z';
  STATE_TRANS pure_outputs
   'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X',
   'D'->'X', 'U'->'X', 'n'->'X', 'N'->'X', 'd'->'X', 'u'->'X',
   '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
   'c'->'H', 'f'->'Z', 'F'->'X';
  STATE_TRANS bidir_inputs
   'D'->'0', 'U'->'1', 'n'->'X', 'N'->'X', 'd'->'0', 'u'->'1',
   '?'->'X', 'A'->'0', 'a'->'0', 'B'->'1', 'b'->'1', 'C'->'X',
   'c'->'X';
  STATE_TRANS bidir_outputs
   'L'->'L', 'H'->'H', 'l'->'L', 'h'->'H', 'T'->'Z', 'x'->'X',
   '?'->'X', 'A'->'H', 'a'->'X', 'B'->'L', 'b'->'X', 'C'->'L',
   'c'->'H', 'f'->'Z', 'F'->'X';
  END
  TVF_BLOCK
  BEGIN
  TARGET_FILE = "expd2.avc";
  TESTER_FORMAT hp93000
   -auto_group,
   TIME_STAMPS = "ON",
   PIN_CONFIG_FILE = "expd2.pins",
   DVC_FILE = "expd2.dvc";
  RESOLUTION 0.001;
  END

          ----------------------------------------------------------------

If the target tester does not have multi-port capabilities, the options are limited. Depending on the requirements of the device, it may be possible to do a multi-pass translation where each pass is associated with an "active" domain. Instead of extracting signals by time domain, all signals are included in each pass and signals in the "inactive" time domains are masked using the MASK_PINS command.

  MASK_PINS MASK_CHARACTER=D domain1_nrzSig1 @ 0 450000;
  MASK_PINS MASK_CHARACTER=X domain1_outSig1 @ 0 450000;

The resulting set of functional test programs can then be concatenated in a separate pass using VTRAN's MERGE_FILE command. See the "Merging Multiple Vector Files" Application Note for more information.

  TABULAR_FORMAT WGL -cycle; {-cycle preserves source cycle structure}
  MERGE_FILE -CONCATENATE
   ORIG_FILE = "progt1.wgl"; {domain1 is active}
  END_MERGE;
  MERGE_FILE
   ORIG_FILE = "progt2.wgl"; {domain2 is active}
  END_MERGE;

VTRAN's TEMPLATE_CYCLIZATION feature is used in the PROC_BLOCK of this final pass to to specify and assign the multiple timesets. Note that the source timesets must be compatible across the merged files. Unique timesets must have unique names and for a given signal, format assignments should remain the same whenever possible.

  TEMPLATE_CYCLIZATION
   TERMINATE_ON_DEFAULTS = "-1",
   MATCH_REPORT = "match.rpt";
   TIMESET T1
    CYCLE 10;
    { PINTYPE statements specify device test specs for domain1 }
    SELECT_RANGE 0 4800; {timeset assignment}
   ENDTIMESET;
   TIMESET T2
    CYCLE 6.766;
    { PINTYPE statements specify device test specs for domain2 }
    SELECT_RANGE 4800 10000; {timeset assignment}
   ENDTIMESET;
   .
   .
   .

Ultimately, it might necessary to regenerate the source vectors with modified cycle times so that they fit into the Case 1 or Case 2 scenarios.

Product Support