Simulate Translate Test

Adding Statements to Target Vector File

This Application Note focuses on the INSERT_STATEMENT feature of the Vtran command file. The INSERT_STATEMENT command can be used to insert statements into the Vtran Target Vector File (TVF) that are not generated by Vtran from data in the Original Vector File (OVF). Comments are one type of statement that can be added with this feature.

There are three different ways to specify where a statement should be added: vector time, and pin state transitions, and compound logic expressions. With cycle-based target formats, the statement can be added before or after a vector.

In addition, the user can specify an optional count that limits the number of times the statement is added.

VTRAN® Overview

The Vtran translation process is divided into three separate tasks or blocks, which correspond to the three blocks in the vtran command file - the OVF_BLOCK, the PROC_BLOCK and the TVF_BLOCK. The commands and parameters in these blocks direct the details of the translation. In general, the OVF_BLOCK contains information necessary for vtran to read the input file or "Original Vector File". The PROC_BLOC contains commands that tell vtran what data processing functions you want performed on the simulation data during translation. This typically would include such functions as how to map state characters between the two formats, dealing with bi-directional data, or perhaps some desired signal masking. Finally, the TVF_BLOCK contains commands that specify the desired output format. There may also be some final processing to be done or some optional user-supplied parameters that appear in the TVF_BLOCK.

The INSERT_STATEMENT command is a part of the Vtran command file PROC_BLOCK.

Insert Statement Feature

The INSERT_STATEMENT command can be used to add statements to the Target Vector File. Vtran does not check the validity of a statement with respect to the TVF syntax. The intention of this feature is to allow arbitrary tester or simulation statements, like subroutine calls, to be placed at specific locations in a test pattern or testbench. This feature also can be used to insert comments for documentation.

The INSERT_STATEMENT command has the following syntax:


    [-before | -after]




    [-before | -after]

    [-count n]

    signal_name state->state;



    [-before | -after]

    [-count n]


The control type field (TIME, TRANSITION, or CONDITION) is required. While a given INSERT_STATEMENT command only has one control type, separate INSERT_STATEMENT commands in a Vtran command file can use different control types.

Each INSERT_STATEMENT command is evaluated individually, for each vector. The CONDITION and TRANSITION controls are evaluated before any state transitions are applied, so any states specified should be states from the Original Vector File.

The location field (-before, -after) is optional, and defaults to -before. For cycle-based output formats (testers, WGL, STIL, etc..) the -before flag causes the statement text to be placed just prior to the vector where the TIME, TRANSITION, or CONDITION occurs. The -after flag causes the statement text to be placed just after the vector. For event-based outputs, such as a testbench, the statement text is inserted within the same event time that the TIME, TRANSITION, or CONDITION occurs.

The count field is optional; the default is to generate all applicable instances of the statement. When the count field is included, only the first n instances of the TRANSITION or CONDITION result in the statement being generated.

A maximum of 1024 INSERT_STATEMENT commands can be specified in a single Vtran command file.

The statement to be inserted is defined inside quotation marks. If the statement spans multiple lines, include the newline character inside the quotation marks; do not use the backslash escape sequence. To include a quotation mark inside the inserted statement, use the backslash sequence (i.e., "... \" ...").

Vtran does not check the validity of the statement. It can include multiple statements in the syntax of the TVF file. It can consist of, or include, one or more comments.

Vector Time

The TIME control type specifies that a statement should be inserted before or after a given vector time. When there is no target vector or event at the defined vector time, the following rules apply:

With the -before flag, the statement will be inserted before the vector or event that precedes the specified time.

Example: For a specified time of 450ns, and vectors at 400ns and 500ns, the -before statement will be before the vector at 400ns.

With the -after flag, the statement will be inserted before the first vector or event that follows the specified time.

Example: For a specified time of 650ns, and vectors at 600ns and 700ns, the -after statement will be before the vector at 700ns.

State Transitions

The TRANSITION control type specifies that a statement should be inserted when a named signal changes state (transitions from one state to another state). The asterisk character "*" represents "any state", so *->1 means any-state-to-logic-1 transitions, and *->* means "any transition".

The states of a transition are those read from the OVF, prior to the application of state translations (STATE_TRANS command).

Compund Logic Expressions

The conditions under which a statement should be inserted might be dependent on the state of the device, A "compound logic expression" can be used to specify the device state that determines when the statement should be inserted into the TVF.

Compound logic expressions are described in Section 2.4 of the Vtran Users Guide. They can include the operators OR (|), AND (&), and NOT (~). They are evaluated left-to-right, unless overridden by parentheses.

The operands of a compound logic expression are pin names and states. The states are those read from the OVF, prior to the application of state translations (STATE_TRANS command). By default, the state for a pin is its value in the current vector, at the time the expression is being evaluated. The user can specify that the pin's state from an earlier or later vector should be used for the expression evaluation, with an optional vector offset. This is accomplished by following the pin name with (+/-n), where n is the number of vectors preceding or following the current vector.

An example of a compound logic expression which is true when pin1 is a logic 1 in the current vector, pin2 was a logic 0 three vectors ago and pin3 is a logic Z in the current vector:

(pin1=1) & ((pin2(-3)=0) | (pin3=Z))

Some Examples

The first example uses the TIME control type:

INSERT_STATEMENT "/* Start of Scan test */" @ TIME -after 250;

This will insert the comment just before the first vector with a cycle time greater than 250ns.

The second example uses the TRANSITION control type:

INSERT_STATEMENT "macro \"MySpecialFunction\" ;"

  @ TRANSITION InData[1] 1->0 ;

This example invokes a macro each time the InData[1] bus member changes state from logic-1 to logic-0. This example includes quotation marks in the inserted statement text. The inserted statement will appear in the TVF as:

macro "MySpecialFunction" ;

The third example uses the CONDITION control type:

INSERT_STATEMENT "call subr_set ;"

  @ CONDITION -count 1,

  (pin1(-4)=1) & (pin2(+8)=0) ;

This will insert the text "call subr_set;" just before the vector where the pin1 signal was a 1 four vectors prior and pin2 is a 0 8 vectors after. It will do this only the first time this condition occurs.

The fourth example uses a multiple-line statement:


"// This is conditional comment.

// It is a multiple-line additon.

// It also includes a \"quoted word\"."

    @ CONDITION -after in1 = 0;

Product Support

Customer Quotes

  • VTRAN® is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with Source III has been positive and their support is extremely responsive and timely.
  • We use VTRAN® to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly.
  • Intrinsix Uses VTRAN® to Speed Vector Translation Flow "I had one customer who used VHDL for RTL, Verilog for gate level simulation, and sometimes used EPIC tools. Getting vectors into the various formats was a nightmare. VTRAN® made the translation process easy and seamless. Plus, WGL or STIL for the test group. Support from Source III has also been quite impressive. In one case, they wrote a bug fix for me in under a day." John Weiland Intrinsix Consultant  
  • Sanera Utilizes Full Featured VTRAN® to Convert Functional and ATPG Vectors "We chose VTRAN® because it can handle multiple simulation file formats (including VCD and WGL) from a single tool. VTRAN's commands are easy to use. The flexibility in pin mapping, masking outputs, and generating scan-based vectors proves to be tremendously helpful. And most of all, Source III provides excellent, fast response to our support needs. This helps us to get things moving very quickly - making good solid progress." Ken ChenTest Engineering Manager
  • Source III VTRAN® tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion
  • We currently use VTRAN for translating WGL, EVCD and VCD vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
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