Simulate Translate Test

Generating Device Test Program Statistics

This Application Note focuses on the CREATE_STATISTICS feature of VTRAN®. Applicable to both cycle-based and print-on-change vector formats, this option accumulates and reports statistics on the state and state transitions of signals in the target vector file. It can be applied to any signal in the VTRAN® translation and is useful during the test program verification process to determine the extent to which signal activity is being checked. Additionally, on cycle based formats, CREATE_STATISTICS options cause VTRAN® to report the total number of cycles and total test time contributed by each timeset.

VTRAN® Overview

The user controls the VTRAN® translation process with an ASCII command file. Historically, the ASCII command file has been created using a text editor and VTRAN® has been launched from the command line. While, this continues to be an option, the VTRAN® User Interface Utility (VUI) is now available. It is a graphical user interface developed specifically for generating VTRAN® command files and is automatically installed with VTRAN® in the S3_ROOT directory. Either way, the concepts and the results are the same.

The three blocks that make up the VTRAN® command file are:

  • OVF_BLOCK - The Original Vector File Block
  • PROC_BLOCK - The Process Block
  • TVF_BLOCK - The Target Vector File Block

The commands and parameters in these blocks direct the details of the translation. In general, the OVF_BLOCK tells VTRAN® how to read the input file or "Original Vector File". VTRAN®'s reader technology enables it to read almost any print-on-change or cycle-based format and includes support for user defined formats. The PROC_BLOCK contains commands that tell VTRAN® the data processing functions to be performed on the simulation data during translation. This typically includes such functions as how to map state characters between the two formats, bi-directional data control, signal masking, and cyclization commands. Finally, the TVF_BLOCK contains commands that specify the desired output format.

The CREATE_STATISTICS command is applied in the TVF_BLOCK.


When generating device test programs for testbench or physical hardware, especially after a cyclization or a MASK_PINS process, it is important to understand the resulting signal activity. CREATE_STATISTICS can be used to monitor the logic states and logic transitions on any signal for all of or part of the vector space in the target vector file. The syntax of the CREATE_STATISTICS command for reporting state information looks like:

CREATE_STATISTICS "filename" pinlist [=] [logic0 state_list,] [logic1 state_list] [start nn] [end nn];

Insert this statement into the VTRAN® ASCII command file* or use the TVF_Block Form in the VUI.

filename is the name of the output file that contains the report.

pinlist is a space or comma separated list of signals to be monitored. The user can select input, output, and bidirectional signals in the pinlist. Pre-defined groups (i.e. INPUTS, OUTPUTS, PURE_INPUTS, PURE_OUTPUTS, BIDIR_INPUTS, BIDIR_OUTPUTS) can be included in the pinlist. If no signals are listed in the pinlist, then no signals will be monitored.

logic0 state_list and logic1 state_list are optional state character value assignments. VTRAN® records the transitions on the signals in the pinlist with respect to the logic0 and logic1 states specified here. The state list is space separated. The default logic0 states are 0 D L. The default logic1 states are 1 U H. Because the statistics are collected after the PROC_BLOCK commands MASK_PINS and STATE_TRANS have been applied, the logic states listed here correspond to those used in the target vector file format. If both logic0 and logic1 states are defined, the first state list must be terminated by a comma. All other states are considered to be intermediate.

start nn and end nn are optional start and end event/cycle times (specified in ns) of the first and last vectors for which statistics should be recorded. By default, statistics will be recorded for all vectors.

*Important: If a DELETE_PINS command is used in the TVF_BLOCK, the CREATE_STATISTICS statement must be placed before the DELETE_PINS statement in the TVF_BLOCK.

Bidirectional Signals

VTRAN® creates two internal pins for each bi-directional signal. The input uses the defined name and is used to store the input data from the OVF. Output data is stored on the output version of the signal "signal.O". During the OVF process, the input is assigned a Z state when the pin direction is determined to be output. Similarly, the output is assigned an X state when the pin direction is determined to be input. Depending on the target format, the states on a bidirectional pin are recombined to a single pin during the generation of the target vector file.

CREATE_STATISTICS is applied before bidirectional signals are merged onto a single pin. If the input part of the signal is not intermediate (i.e. Z or X), and the output part of the signal is intermediate (i.e. Z or X), the signal is considered to have an input state. If the input part of the signal is intermediate, and the output part of the signal is not intermediate, the signal is considered to have an output state. Signal activity on bidirectional signals where there are simultaneous intermediate states on both the input and output parts are ignored.


  • When used with cycle-based Target Vector Formats with separate timing, input transitions are based on state values only. That is, level transitions that occur as part of the signals' timing format or parameterized waveform description are not included in the accumulated statistics.
  • There is no transition at time 0.
  • Compare state statistics on outputs are collected for each count on a repeated vector.
  • Transition data on inputs and bidirectionals are counted only once on a repeated vector.
  • Scan vector data is not included in these statistics. For scan cycles, data is collected on signal parallel states only.
  • Compare and transition data is collected only once per loop regardless of loopcount.

An Example

Here is an example TVF_BLOCK with a CREATE_STATISTICS command applied to the first 25000 ns of the target vector file "exp.wgl". Predefined signal groups inputs and outputs are used to specify all signals. logic0 and logic1 states are assigned default values 0 D L and 1 U H respectively. Accumulated data appears in the file named "tp.rpt".

    CREATE_STATISTICS "tp.rpt" inputs,outputs = start 0, end 25000;
      AddressElement = "CycleNumber";
    TARGET_FILE = "exp.wgl";

The Report

The report of the accumulated statistics for state data is divided into 3 sections. The first section reports state data for outputs and the output side of bidirectional signals. The entries list the number of compares to a logic 1 state, the vector/cycle time of the first comparison, the number of compares to a logic 0 state, and the vector/cycle time of the first comparison. If the TVF is print-on-change, consecutive vectors with a logic-0 or logic-1 state will be counted as a single compare. If the TVF is cycle-based, each vector will count as a single compare.

The second section reports state data for inputs and the input side of bidirectional signals. The entries list the number of transitions to a logic 1 state, the vector/cycle time of the first of these transitions, the number of transitions to a logic 0 state, and the vector/cycle time of the first of these transitions. A transition from intermediate states (such as X or Z) will be counted only if preceded by the opposite state. As stated earlier, on cyclized data, these statistics do not include transitions that are part of a waveform for clock signals. For clock signals a transition to a logic 1 or 0 will represent the enabling or disabling of the clock.

The last section details changes in direction on bidirectional signals. The entries list the number of transitions from an output state to an input state, the vector/cycle time of the first of these transitions, the number of transitions from an input state to an output state, and the vector/cycle time of the first of these transitions.


                 logic 1          logic 0

  Signal Name  (first compare) (first compare)

  -----------  --------------- ---------------

  "data0.O"    0               0

  "data1.O"    10 (5000ns)     0

  "data2.O"    5 (5000ns)      5 (5100ns)

  "outSig1"    0               10 (100ns)

  "outSig2"    0               10 (100ns)

  "outSig3"    5 (5100ns)      5 (100ns)

  "outSig4"    5 (100ns)       5 (5100ns)

               transitions to logic 1 transitions to logic 0

  Signal Name  (first transition)     (first transition)

  -----------  ---------------------- ----------------------

  "address1"   1 (5000ns)             1 (1000ns)

  "address2"   1 (5200ns)             0

  "address3"   9 (200ns)              10 (100ns)

  "address4"   0                      0

  "OE"         0                      1 (5000ns)

  "data0"      1 (100ns)              0

  "data1"      0                      0

  "data2"      0                      0

  "CLOCK"      4 (2000ns)             4 (1200ns)

              transitions to input transitions to output

  Signal Name  (first transition)     (first transition)

  ----------- -------------------- ---------------------

  "data0"     0                    0

  "data1"     0                    1 (5000ns)

  "data2"     0                    1 (5000ns)

This report indicates possible worrisome situations:

  • no directional activity or meaningful strobes on bidir signal "data0"
  • only logic 0 compare values on output signals "outSig1" and "outSig2"
  • only logic 1 compare values on bidir signal "data1"
  • no input transitions on input signal "address4" or bidir signals "data1" and "data2"

When the TVF is cycle-based, the CREATE_STATISTICS parameter "-INCLUDE_TIME_STATS" causes VTRAN® to collect and report timeset statistics.

CREATE_STATISTICS "filename" -INCLUDE_TIME_STATS [=] [start nn] [end nn];

When specified, timeset names, period values, cycle counts, and the total test time contributed by each timeset is presented in the report file. If start/end times are specified then the timeset statistics are accumulated, inclusively, for the time range specified.

Special Situations

  • VTRAN® supports the MERGE_TSETS (MERGE TimeSETS) directive on translations where the target format uses WaveForm Charaters as pattern characters in vector statements. In this case, statistics are provided for the original timesets and the definitions of the merged timesets are output separately for reference.
  • Timeset statistics on pad vectors inserted into the TVF by the VTRAN® XMODE command are reported separately and always for the entire pattern regardless of start/end times.

An Example

The following is an example of how to use CREATE_STATISTICS to cause VTRAN® to collect only timeset statistics in the target vector file "vtran3.avc".

      TARGET_FILE = "vtran3.avc";
         MAX_LINE_LENGTH = "80"
         TIME_STAMPS = "On"
         DVC_FILE = "vtran3.dvc"
      RESOLUTION = 1.0;

The Report

See an example of the TIMESET STATISTICS report below. In this case, the relatively few occurrences of the "base2" timeset may indicate an opportunity to conserve tester resources.

TIMESET NAME:    base1
TOTAL TIME:      115600ns

TIMESET NAME:    base2
TOTAL TIME:      800ns

TIMESET NAME:        base1
TIMESET PERIOD:      400ns
TOTAL PAD TIME:      400ns


VTRAN can be used to create a VERILOG Testbench from either print-on-change or cyclized OVF files. If the -VECTOR_COUNT option is specified in the SIMULATOR statement of the TVF_BLOCK, VTRAN includes VERILOG statements that annotate compare failures with vector count, cycle number, active timeset value, and in the case of MERGE_FILE usage, the name of the OVF source. When the Original Vector File is a test program or some other cyclized format (i.e. STIL, WGL, etc...) and CREATE_STATISTICS is specified, the -VECTOR_COUNT option causes the statistics report to also include the Total Vectors and Total Cycle Count observed in this file.

An Example

      TARGET_FILE = "tc1.tb";
         TESTBENCH_MODULE = "design_module"
         COMPONENT_MODULE = "design"
         INSTANCE_NAME = "design_inst"
         TIMESCALE = "1ns / 1ns"
         TERMINATE_RUN = "$stop"
      CREATE_STATISTICS "stat.txt" inputs, outputs, bidir_inputs, bidir_outputs;

Other examples of the CREATE_STATISTICS command are:

{# Collect strobe for all outputs over all vectors/cycles}

	CREATE_STATISTICS "tp.rpt" outputs;

{#Collect strobe for signal outSig1 beginning at 100ns.
    Regard post STATE_TRANS values 1,H,Z as logic1}

	CREATE_STATISTICS "tp.rpt" outSig1 = logic1 1 H Z, start 100;

{# Collect strobe values on "outSig1" over all vectors/cycles}

	CREATE_STATISTICS "tp.rpt" outSig1;

{# Collect strobe values on bidir signals between 200ns and 218600ns.
     #Regard post STATE_TRANS values S,0,L,Z states as logic0.
     #Regard post STATE_TRANS values M,1,H as logic1}

	CREATE_STATISTICS "tp.rpt" bidir_inputs, bidir_outputs 
		= logic0 S 0 L Z, logic1 M 1 H, 
		start 200 end 218600 ;

{# Collect timeset and state data on all signals, over all vectors/cycles}


{# Collect timeset data up to and including the vector/cycle beginning at 10000ns}


See the "VTRAN® User Guide" and the "VUI VTRAN® User Interface Guide" for more details on using these and other VTRAN® commands.

Product Support

Customer Quotes

  • We use VTRAN® to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly.
  • Intrinsix Uses VTRAN® to Speed Vector Translation Flow "I had one customer who used VHDL for RTL, Verilog for gate level simulation, and sometimes used EPIC tools. Getting vectors into the various formats was a nightmare. VTRAN® made the translation process easy and seamless. Plus, WGL or STIL for the test group. Support from Source III has also been quite impressive. In one case, they wrote a bug fix for me in under a day." John Weiland Intrinsix Consultant  
  • We currently use VTRAN for translating WGL, EVCD and VCD vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
  • Source III VTRAN® tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion
  • VTRAN® is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with Source III has been positive and their support is extremely responsive and timely.
  • Sanera Utilizes Full Featured VTRAN® to Convert Functional and ATPG Vectors "We chose VTRAN® because it can handle multiple simulation file formats (including VCD and WGL) from a single tool. VTRAN's commands are easy to use. The flexibility in pin mapping, masking outputs, and generating scan-based vectors proves to be tremendously helpful. And most of all, Source III provides excellent, fast response to our support needs. This helps us to get things moving very quickly - making good solid progress." Ken ChenTest Engineering Manager
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