Simulate Translate Test

Adding New Pins to Target Vector File

This Application Note focuses on the ADD_PIN feature of the Vtran command file. The ADD_PIN command can be used to insert pins into the Vtran Target Vector File (TVF) that are not defined in the Original Vector File (OVF). There are three attributes of an added pin: pin name, and pin direction, and pin waveform information. The pin name and waveform information must be defined by the user; the pin direction defaults to INPUT, but can be overridden by the user. Vtran provides several mechanisms for the user to define the pin's waveform. This Application Note will emphasize issues relevant primarily to defining the pin's waveform.

VTRAN® Overview

The Vtran translation process is divided into three separate tasks or blocks, which correspond to the three blocks in the vtran command file - the OVF_BLOCK, the PROC_BLOCK and the TVF_BLOCK. The commands and parameters in these blocks direct the details of the translation. In general, the OVF_BLOCK contains information necessary for vtran to read the input file or "Original Vector File". The PROC_BLOC contains commands that tell vtran what data processing functions you want performed on the simulation data during translation. This typically would include such functions as how to map state characters between the two formats, dealing with bi-directional data, or perhaps some desired signal masking. Finally, the TVF_BLOCK contains commands that specify the desired output format. There may also be some final processing to be done or some optional user-supplied parameters that appear in the TVF_BLOCK.

The ADD_PIN command is a part of the Vtran command file PROC_BLOCK.

ADD_PIN Feature

The ADD_PIN command can be used to add pins with a constant state, pulsing clocks, and pins whose state depends on the state of one or more other pins.

The ADD_PIN command has the following syntax:

ADD_PIN pin_name

  [input | output | bidir]

  [LINK_TIMING link_pin_name]

  = state(s) [WHEN compound_logic_expr :

  = state WHEN compound_logic_expr :

  ...

  = state OTHERWISE];

The pin_name field is required. The direction field is optional, and defaults to input. The optional LINK_TIMING field is associated with cycle-based translations and is discussed in detail below. A state must be specified. There are several mechanisms for doing this, and they are enumerated and then explained below.

A maximum of 16 different states can be specified for a given added pin.

Bidirectional pins can have two states specified, one for input and one for output. These must be specified as fixed states. This restriction only applies to bidirectional pins.

Compound Logic Expressions

The state of an added pin might be dependent on the state of the device, and take on different values at different times. A "compound logic expression" can be used to specify the device state that determines when the added pin takes a given state value.

Compound logic expressions are described in Section 2.4 of the Vtran Users Guide. They can include the operators OR (|), AND (&), and NOT (~). They are evaluated left-to-right, unless overridden by parentheses.

The operands of a compound logic expression are pin names and states. The states are those read from the Original Vector File, prior to the application of state translations (STATE_TRANS command). By default, the state for a pin is its value in the current vector, at the time the expression is being evaluated. The user can specify that the pin's state from an earlier or later vector should be used for the expression evaluation, with an optional vector offset. This is accomplished by following the pin name with (+/-n), where n is the number of vectors preceding or following the current vector.

DEFINING PIN'S STATE VALUE

The ADD_PIN command can be used to define a fixed state for the pin, or a state dynamically defined by the state of other pins.

The fixed state is the simplest way to define an added pin's state value. If no other command is used to specify the timing or format of the pin, the pin holds the defined state for the entire test.

As described in the next section, other Vtran commands can be used to define timing or format values for the pin. If so, the fixed state specifed in the ADD_PIN command represents the state the pin would have had in each vector. The other commands determine how this state is applied to a waveform for the pin. This approach can be used to add a clock that pulses in every cycle, for example.

When the pin does not have a single fixed state, the state of one or more other pins is used to define the state of the new pin for a given vector. For each state the new pin can have, a conditional clause defines the device state that selects a given state value. For each new pin, a single, optional OTHERWISE clause selects a default state.

DEFINING PIN'S TIMING AND FORMAT

There are four mechanisms available to define the timing, and possibly the format, of an added pin that does not have a constant state for the entire test:

  • The PIN_TYPE command
  • The EDGE_SHIFT command
  • The EDGE_ALIGN command
  • The LINK_TIMING feature of the ADD_PIN command

When the added pin's state is defined as a fixed state in the ADD_PIN command, the PINTYPE command can be used. This command defines the pin's timing and format in the Target Vector File. Allowed PINTYPE formats for an added pin are: RZ, RO, RX, RZ2X, and RO2X. This definition can be used both for print-on-change and cycle-based target vector formats. Since the edge times in the PINTYPE command are relative to a cycle boundary, the CYCLE command must be included if the cycle time value is not defined by the OVF.

When the added pin's state is defined in terms of the states of other pins in the ADD_PIN command, the EDGE_SHIFT and EDGE_ALIGN commands can be used. These commands are applicable to print-on-change OVF to print-on-change TVF translations. The timing commands modify the edge times of the new pin's transitions in the Target Vector File. In the absence of these timing commands, the pin would have a transition in the TVF at the time a change in state of the other pins changes its evaluated state. Since the edge times in the EDGE_ALIGN command are relative to a cycle boundary, the CYCLE command must be included if it is used.

For translations to cycle-based target vector formats, the LINK_TIMING option of the ADD_PIN command can be used to specify that the added pin's timing matches that of an existing pin. This is applicable to a pin with either a fixed-state or a dynamically-defined state.

When the TEMPLATE_CYCLIZATION block is used to convert a print-on-change OVF to a cycle-based TVF with multiple timesets, the TIMESETs defined in the block cannot be used to specify timing for added pins. If there is an existing pin whose timing matches the added pin in all timesets, the LINK_TIMING field of the ADD_PIN command can be used to specify that the existing pin be used to define the timing for the added pin. This does not, however, specify a format for the new pin, which defaults to NRZ. If the added pin has the same timing and format in all timesets, the PINTYPE command can be used in addition to the TEMPLATE_CYCLIZATION block to specify the new pin's timing and format. Note that in this case, the CYCLE command is not required.

Also, when translating from cycle-based formats like WGL or STIL where there are multiple timesets defined for signals, the LINK_TIMING field can be used to associate the new signal timing with an existing one in the input file timesets.

Some Examples

For a clock pin whose state is defined as a fixed state by the ADD_PIN command, its format (RZ) and edge times can be specified by the PINTYPE command to cause the pin to pulse in each cycle:

CYCLE 250;

ADD_PIN newClk1 = 1;

PINTYPE RZ newClk1 @ 125, 200;

For a bidirectional pin whose state is defined as a fixed state by the ADD_PIN command, its format (RO2X) and edge times can be specified by the PINTYPE command to cause the pin to double-pulse in each cycle:

CYCLE 100;

ADD_PIN newBidir1 bidirect = 0X;

PINTYPE RO2X newBidir1 @ 15, 30, 45, 60;

The output side of this bidirectional pin is masked in each cycle.

For a bidirectional pin whose state is defined as a fixed state by the ADD_PIN command, its strobe times can be specified by the PINTYPE command to cause the pin to be compared in each cycle:

CYCLE 100;

ADD_PIN newBidir2 bidirect = Z1;

PINTYPE STB newBidir2.O @ 30, 60;

The driver of the input side of this bidirectional pin is off in all cycles.

For a clock whose state and edge times are based on an existing clock, its state is defined with the WHEN and OTHERWISE features of the ADD_PIN, while its edge times are specified with the EDGE_SHIFT command:

ADD_PIN newClk2 = 0 WHEN clk=1 :

  = 1 OTHERWISE;

EDGE_SHIFT newClk2 @ 5, -5, 0;

This results in a non-overlapping complement of the existing "clk" pin.

The clock in the previous example can have its edge times defined by the EDGE_ALIGN command:

CYCLE 50;

ADD_PIN newClk2 = 0 WHEN clk=1 :

  = 1 OTHERWISE;

EDGE_ALIGN newClk2 @ 20, 35, 0;

This results in a non-overlapping complement of the existing "clk" pin.

For a clock pin whose state is defined as a fixed state by the ADD_PIN command, its edge times can be specified by the LINK_TIMING option to match an existing clock, causing the new pin to pulse in each cycle:

ADD_PIN newPin1 LINK_TIMING clkPin

   = 1;

This must be a translation to a cycle-based TVF.

The following example shows how to define a new pin whose state depends dynamically on the states of other pins. The LINK_TIMING option is used to specify its timing behavior, based on the timing of an existing pin.

        

ADD_PIN newPin2 LINK_TIMING alignPin

   = 0 WHEN Mode[0]=0 :

   = 1 WHEN (Mode[0]=1)&(Mode[1]=1) :

   = Z OTHERWISE;

This must be a translation to a cycle-based TVF.

The following example uses the vector-offset feature of the compound logic expression to define the conditions under which the new pin takes a given state:

ADD_PIN newPin3

   = 0 WHEN (ctrl(-3)=1)&(enb(2)=0) :

   = 1 WHEN (ctrl(-2)=1)&(enb(1)=0) :

   = X WHEN (ctrl(-1)=1)|(enb=0) :

   = Z OTHERWISE;

The new pin's state is 0 when "ctrl" pin's state is 1 three vectors prior to the current vector, and "enb" pin's state is 0 two vectors after the current vector. The new pin's state is 1 when "ctrl" pin's state is 1 two vectors prior to the current vector, and "enb" pin's state is 0 one vector after the current vector. The new pin's state is X when "ctrl" pin's state is 1 one vector prior to the current vector, or "enb" pin's state is 0 in the current vector. If none of these conditions is met, the new pin's state is Z.

In the following TEMPLATE_CYCLIZATION example, where a print-on-change OVF is translated to a cycle-based TVF with multiple timesets, an existing pin is used to define the timing behavior of the new pin in each timeset:

ADD_PIN newClk3 LINK_TIMING nclk = 0;

TEMPLATE_CYCLIZATION

  MATCH_REPORT = "match.rpt";

TIMESET ts1

  CYCLE 25;

  PINTYPE RO nclk @ 10, 20;

  ...

ENDTIMESET;

TIMESET ts2

  CYCLE 35;

  PINTYPE RO nclk @ 15, 25;

  ...

ENDTIMESET;

TIMESET ts3

  CYCLE 45;

  PINTYPE RO nclk @ 20, 30;

  ...

ENDTIMESET;

In the following TEMPLATE_CYCLIZATION example, where a print-on-change OVF is translated to a cycle-based TVF with multiple timesets, the PINTYPE command is used to define the timing behavior of the new pin in all timesets:

ADD_PIN newClk3 = 0;

TEMPLATE_CYCLIZATION

  MATCH_REPORT = "match.rpt";

TIMESET ts1

  CYCLE 25;

  ...

ENDTIMESET;

TIMESET ts2

  CYCLE 35;

  ...

ENDTIMESET;

TIMESET ts3

  CYCLE 45;

  ...

ENDTIMESET;

PINTYPE RO newClk3 @ 10, 20;

Product Support

Customer Quotes

  • We currently use VTRAN for translating WGL, EVCD and VCD vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
  • Intrinsix Uses VTRAN® to Speed Vector Translation Flow "I had one customer who used VHDL for RTL, Verilog for gate level simulation, and sometimes used EPIC tools. Getting vectors into the various formats was a nightmare. VTRAN® made the translation process easy and seamless. Plus, WGL or STIL for the test group. Support from Source III has also been quite impressive. In one case, they wrote a bug fix for me in under a day." John Weiland Intrinsix Consultant  
  • VTRAN® is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with Source III has been positive and their support is extremely responsive and timely.
  • Source III VTRAN® tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion
  • Sanera Utilizes Full Featured VTRAN® to Convert Functional and ATPG Vectors "We chose VTRAN® because it can handle multiple simulation file formats (including VCD and WGL) from a single tool. VTRAN's commands are easy to use. The flexibility in pin mapping, masking outputs, and generating scan-based vectors proves to be tremendously helpful. And most of all, Source III provides excellent, fast response to our support needs. This helps us to get things moving very quickly - making good solid progress." Ken ChenTest Engineering Manager
  • We use VTRAN® to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly.
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