Simulate Translate Test

Customer Support Question: Converting STIL to HP93000K

Sunday, 30 April 2017 16:11

Our Support Team is always available to help our clients with their vector conversion needs. Sometimes, we receive a question that is applicable to both current and future clients, and we share it here on the website. The following is a question about spaces between signals, and how to remove them during conversion with VTRAN.

Question: I’m using a canned reader for STIL patterns, and converting them to HP93000K format. After the conversion, the pattern looks like this:

XXXXXXXX XXXX XXXXXXZZ 0 0 00 1 1 0 0 ; 1200

XXXXXXXX XXXX XXXXXXXZ 0 0 01 1 1 0 1 ; 1600

XXXXXXXX XXXX XXXXXZZZ 0 0 00 1 0 0 1 ; 2000

XXXXXXXX XXXX XXXXXXXZ 0 0 01 1 0 0 0 ; 2400

XXXXXXXX XXXX XXXZZZZZ 0 0 00 1 1 1 0 ; 2800

There is a space between each signal, and group of signals, which are enumerated bits of a bus. How do I tell VTRAN not to add any space?


To control the spacing of individual signals, you can use the -AUTO_GROUP option to the TESTER_FORMAT statement (in the TVF Block) to automatically group busses together. If you omit this option you can insert as many or as few spaces as you want between signals.

We have developed step by step instructions that explain the process in detail on this post, which explains how to separate the clocks from the busses without resorting to post-processing.