Simulate Translate Test

QA: VTRAN Support for RZ4X Pintypes in uFLEX patterns?

Thursday, 20 April 2017 22:27

Source III provides constant support for all our clients. If you have any questions about our software, or how to perform a task, please do not hesitate to email us directly at This email address is being protected from spambots. You need JavaScript enabled to view it.. On occasion, we receive emails from our clients that may be relevant to a larger audience. The following is a question we received about RZ4X Pintypes.

Question: Can VTRAN support RZ4X pintypes when adding a new pin to uFLEX patterns?

Answer: We don't believe the uFLEX handles RZ4X waveforms directly.  VTRAN currently supports that clock format only for translations to the Advantest V93000 ATE (SmarTest 7 and 8) as well as to STIL files. 

If you want a free running clock (i.e. is always running through the entire pattern) you can use the FreeRunningClock statement in the TVF_BLOCK.  This must  be placed *after* the TESTER_FORMAT statement and options, and to pulse 4 times a cycle (40ns cycle) would look something like:

TVF_BLOCK

BEGIN

    TESTER_FORMAT teradyne -ULTRAFLEX

    -USE_TSET_NAMES

    ... etc ...

    WR_TIMESET_FILE = "outfile";

    FreeRunningClock input RZ clk_fast RZ 10.0, 0.0, 5.0;

   . . . . .

END;

This will create a clock which pulses every 10ns, with a rising edge at 0ns and a falling edge at 5ns - in other words a clock which pulses 4 times in a 40ns cycle.   The clock will have no entry in the vector file and hence it is always running; the basic timing file "outfile_basic_ts.txt" will define the clock.

The VTRAN User Guide pp436-437 has more detailed information on adding free running clocks for Teradyne formats.  Note: you'll need VTRAN 10.1 or newer to avail of this feature.