Simulate Translate Test

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and Source III, Inc., a leading developer of test conversion and verification programs, have announced a collaboration to enable improved test validation and faster test conversion for enhanced chip quality. The joint effort expands the silicon design chain to include validation by Source III of test programs developed on the Cadence® Encounter® Test automated test program generation (ATPG) platform, as well as conversion of semiconductor test programs to targeted automatic-test-equipment (ATE) platforms. Source III will validate test programs generated on the Encounter Test platform using Verilog model simulations as the golden standard. Additionally, Source III will convert and generate test programs from the Cadence standard test interface language STIL to a format readable by targeted ATE platforms. Continued in PDF
The 7.6 release of vtran provides significant enhancements to the STIL interfaces, both canned reader module and the STIL output formatter. The ReadBack modules from previous releases have been enhanced to provide cycle-based readback as well as the event-based capabilities. This means that vtran-generated test programs can be directly translated to other tester formats as well as testbench formats for verification. The Agilent (HP) 93000 interface has been enhanced to handle Pincsale capabilities with optimized resource assignments in the dvc files. In addition, numerous new parameters have been added to different interfaces to improve user control and customization of the translated vector data.
The 7.1 release of vtran continues to strengthen the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. This release introduces additional canned reader modules called Read-Back modules which provide a new, efficient way to verify vtran-generated test programs prior to loading them on a tester. These modules can be used by vtran to directly read-back the test programs and then generate a Verilog or VHDL testbench for a re-simulation verification check. Read-Back support for Credence, Agilent (HP93000), Teradyne J750, J973 and Catalyst are included in this release. XMODE support for the Agilent 93000 tester is now available, enabling significant memory size and performance improvements.
The 7.0 release of vtran strengthens the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. This release introduces a new set of canned reader modules called Read-Back modules which provide a new, efficient way to verify vtran-generated test programs prior to loading them on a tester. These modules can be used by vtran to directly read-back the test programs and then generate a Verilog or VHDL testbench for a re-simulation verification check. Read-Back support for Credence, Agilent (HP93000), Teradyne J750 and Catalyst are included in this release. The STIL reader has also undergone substantial upgrades in this release, adding support for many of the popular 1450.1 features needed to handle today's complex SOC designs.

Source III Announces Release 6.5 of VTRAN®

Wednesday, 02 April 2003 10:00
The 6.5 release of vtran introduces the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. Thus, popular VCD files with dynamically changing timing can now be translated to test programs using this feature. Also in this release is initial support for the ITS900 tester. Other new features include enhanced signal masking capabilities, dramatically improved WGL reader performance, a new PIN_INFO_FILE feature, and numerous interface enhancements and upgrades.