Simulate Translate Test

Source III / Synopsys Provide Joint Solution

Friday, 01 September 2000 11:01
Source III joins Synopsys' In-Sync Program to provide a joint solution for quick and easy translation of TetraMAX-generated vectors in either WGL or STIL format to test programs for Credence, Teradyne and HP testers. Using vtran, users can readily translate large scan-based vector sets generated by ATPG products into ready-to-use test programs. Click here for more details.
With the release of VTRAN® 4.6, Source III announces support for the HP83000 and HP93000 testers as target formats for vector translations from WGL, STIL, Verilog VCD and many other formats. With this new interface, the popular HP testers become easily accessible to users with almost any simulation or ATPG-generated vector sets.

Source III Releases VTRAN® 4.6

Tuesday, 01 August 2000 07:02
Source III announces the release of VTRAN® 4.6 with several enhancements to vector translations and support for several new tester formats. With this release, VTRAN® now fully supports translations of vector data which include scan chains and scan-formatted data from the popular WGL, as well as the new IEEE STIL, vector formats to the Teradyne (Catalyst and J750), Credence, HP83000/93000 and HP-3070 (PCF) tester formats, as well as numerous ASIC (TSTL2, TDL_91, ..) and simulator formats (Verilog/VHDL testbench, ..). One of the primary focuses of this new release was the enhanced support of scan data during translation between popular simulator and tester formats. This is an increasingly more common need as scan-based DFT and ATPG tools, such as Synopsys' Design Compiler and new TetraMAX(tm), create vector sets for large complex designs. Support for additional tester formats are planned for release over the next year.

Source III Announces enhanced STIL support

Tuesday, 01 August 2000 03:03
The latest 4.6 Release of VTRAN® now includes support for reading the new IEEE Standard Test Interface Language (1450) vector files. With this improved canned reader, VTRAN® can handle translations from STIL to a variety of testers (including Teradyne, Credence, HP83000/93000 and HP-3070 PCF), ASIC formats such as TSTL2 and TDL_91, and simulator formats such as Verilog and VHDL testbenches. As tools that generate vector data begin to standardize on this new IEEE standard format, the need for a bridge to the numerous other formats accepted by today's simulation tools and testers increases. In addition to providing this bridge, VTRAN® also can be effectively used for verifying tools that generate STIL by providing a path back to simulation - essentially closing the loop. A STIL writer is also under development for release next year.