Source III announces the release of VTRAN® 4.6 with several enhancements to vector translations and support for several new tester formats. With this release, VTRAN® now fully supports translations of vector data which include scan chains and scan-formatted data from the popular WGL, as well as the new IEEE STIL, vector formats to the Teradyne (Catalyst and J750), Credence, HP83000/93000 and HP-3070 (PCF) tester formats, as well as numerous ASIC (TSTL2, TDL_91, ..) and simulator formats (Verilog/VHDL testbench, ..). One of the primary focuses of this new release was the enhanced support of scan data during translation between popular simulator and tester formats. This is an increasingly more common need as scan-based DFT and ATPG tools, such as Synopsys' Design Compiler and new TetraMAX(tm), create vector sets for large complex designs. Support for additional tester formats are planned for release over the next year.