Simulate Translate Test

The 7.0 release of vtran strengthens the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. This release introduces a new set of canned reader modules called Read-Back modules which provide a new, efficient way to verify vtran-generated test programs prior to loading them on a tester. These modules can be used by vtran to directly read-back the test programs and then generate a Verilog or VHDL testbench for a re-simulation verification check. Read-Back support for Credence, Agilent (HP93000), Teradyne J750 and Catalyst are included in this release. The STIL reader has also undergone substantial upgrades in this release, adding support for many of the popular 1450.1 features needed to handle today's complex SOC designs.

Source III Announces Release 6.5 of VTRAN®

Wednesday, 02 April 2003 10:00
The 6.5 release of vtran introduces the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. Thus, popular VCD files with dynamically changing timing can now be translated to test programs using this feature. Also in this release is initial support for the ITS900 tester. Other new features include enhanced signal masking capabilities, dramatically improved WGL reader performance, a new PIN_INFO_FILE feature, and numerous interface enhancements and upgrades.

Source III Announces Release 6.0 of VTRAN®

Friday, 01 February 2002 10:00
The new 6.0 release of vtran enhances a number of interfaces including the following; STIL reader adds support for many .1 (dot 1) extensions, MUX support for WGL, passing of structural loops and repeats between formats, enhanced Verilog and VHDL testbench features plus many more. An initial IMS MEM output format is included in this release. Also this release includes the first 64-bit Solaris version of vtran, pushing its ability to handle very large files beyond the 2GB limit.. With this release, Source III continues its constant improvements and feature enhancements of vtran, based upon customer needs and requests.

Source III Announces release of VTRAN® 5.0

Thursday, 01 February 2001 10:01
This new release of VTRAN® adds support for the Teradyne J971 and J973 testers, in addition to significant enhancements to signal masking processing and the direct reading of gzip'ed files. A new interface to the HSIM simulator from Nassda is also included in this release. The Verilog and VHDL testbench interfaces were both enhanced with additional optional parameters to further customize testbenches.

Source III / Synopsys Provide Joint Solution

Friday, 01 September 2000 11:01
Source III joins Synopsys' In-Sync Program to provide a joint solution for quick and easy translation of TetraMAX-generated vectors in either WGL or STIL format to test programs for Credence, Teradyne and HP testers. Using vtran, users can readily translate large scan-based vector sets generated by ATPG products into ready-to-use test programs. Click here for more details.