The 7.1 release of vtran continues to strengthen the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. This release introduces additional canned reader modules called Read-Back modules which provide a new, efficient way to verify vtran-generated test programs prior to loading them on a tester. These modules can be used by vtran to directly read-back the test programs and then generate a Verilog or VHDL testbench for a re-simulation verification check. Read-Back support for Credence, Agilent (HP93000), Teradyne J750, J973 and Catalyst are included in this release. XMODE support for the Agilent 93000 tester is now available, enabling significant memory size and performance improvements.