Simulate Translate Test

New VTRAN® 9.1 Release

Tuesday, 01 December 2009 09:46
Source III announces the release of VTRAN® 9.1 for the Solaris SPARC, Solaris X86 and Linux platforms. This new release continues our commitment to timely and continuous product improvements in response to the ever-changing needs of our customers. Featured in this release are the following: Enhanced tester interface for the Advantest T2000 tester adding support for scan data on both the T2000 writer and ReadBack module. Enhanced general purpose IDDQ insertion mechanism which can insert up to 3 control signals and user-defined IDDQ vectors at IDDQ markers in WGL and STIL files. Enhanced Verilog testbench output formatters to include vector and cycle count information which corresponds to vectors in the input source file. Very useful when using ReadBack modules for Teradyne, Verigy or Credence to validate test programs. Enhanced TSTL2 writer to better support various combinations of signal grouping and timing. Enhanced MERGE_FILE feature to give more flexibility handling timing…
Source III and the China Electronics Standardization Institute (CESI) announce an agreement whereby CESI will provide sales and technical support for all of Source III's products in mainland China. CESI provides comprehensive services and support of electronic information technology and is under the MII (Ministry of Information Industry). It is located in Beijing with two offices there: Sales contact Main Office: Zhong Weijun No. 1 An Ding Men Dong Da Jie Beijing, P.R. China, 100007 Tel: +86-010-84029279 Fax: +86-010-84029104 Sales contact Yizhuang Industrial Park Office: Zhong Mingchen Tel: +86-010-67831826 Fax: +86-010-67831823 E-mail: This email address is being protected from spambots. You need JavaScript enabled to view it. Personnel from the Electronic Measurement and Calibration Center of CESI have very broad expertise in design and test. This expertise will be very valuable in supporting Source III's products there.
Brugge, Belgium / El Dorado Hills, CA, USA  Q-Star Test nv., the premier supplier of advanced high speed and high accurate IDD test and measurement solutions, and Source III, Inc., a leading developer of test conversion and verification programs, announce a strategic partnership and collaboration to enable reducing test engineering efforts, improved test validation and faster test conversion for enhanced chip quality. Q-Star Test offers IDDX and ISSX monitor solutions, supporting true IDDQ, delta IDDQ, IDDT and analog IDD and the complementary ISSx test strategies applicable to digital, analog, and mixed signal circuits. Q-Star Test's measurement hardware is ATE independent and outperforms other available ATE related IDD test hardware by at least a factor of 100 (with respect to measurement speed and accuracy). The hardware solutions are complemented with application and test strategy related consulting and training services. Source III Simulation and Test Data Management tools provide for quick and…
Magma Design Automation, a provider of chip design software, announced that it has partnered with Source III to offer a direct path from Talus ATPG and Talus ATPG-X to a variety of testers via Source III's VTRAN. With a foundation in IEEE 1450 STIL and through its collaboration with Source III, Magma is working to improve test quality, streamline test flow and reduce test costs. Continued in PDF 
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and Source III, Inc., a leading developer of test conversion and verification programs, have announced a collaboration to enable improved test validation and faster test conversion for enhanced chip quality. The joint effort expands the silicon design chain to include validation by Source III of test programs developed on the Cadence® Encounter® Test automated test program generation (ATPG) platform, as well as conversion of semiconductor test programs to targeted automatic-test-equipment (ATE) platforms. Source III will validate test programs generated on the Encounter Test platform using Verilog model simulations as the golden standard. Additionally, Source III will convert and generate test programs from the Cadence standard test interface language STIL to a format readable by targeted ATE platforms. Continued in PDF