Simulate Translate Test

Brugge, Belgium / El Dorado Hills, CA, USA  Q-Star Test nv., the premier supplier of advanced high speed and high accurate IDD test and measurement solutions, and Source III, Inc., a leading developer of test conversion and verification programs, announce a strategic partnership and collaboration to enable reducing test engineering efforts, improved test validation and faster test conversion for enhanced chip quality. Q-Star Test offers IDDX and ISSX monitor solutions, supporting true IDDQ, delta IDDQ, IDDT and analog IDD and the complementary ISSx test strategies applicable to digital, analog, and mixed signal circuits. Q-Star Test's measurement hardware is ATE independent and outperforms other available ATE related IDD test hardware by at least a factor of 100 (with respect to measurement speed and accuracy). The hardware solutions are complemented with application and test strategy related consulting and training services. Source III Simulation and Test Data Management tools provide for quick and…
Magma Design Automation, a provider of chip design software, announced that it has partnered with Source III to offer a direct path from Talus ATPG and Talus ATPG-X to a variety of testers via Source III's VTRAN. With a foundation in IEEE 1450 STIL and through its collaboration with Source III, Magma is working to improve test quality, streamline test flow and reduce test costs. Continued in PDF 
Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and Source III, Inc., a leading developer of test conversion and verification programs, have announced a collaboration to enable improved test validation and faster test conversion for enhanced chip quality. The joint effort expands the silicon design chain to include validation by Source III of test programs developed on the Cadence® Encounter® Test automated test program generation (ATPG) platform, as well as conversion of semiconductor test programs to targeted automatic-test-equipment (ATE) platforms. Source III will validate test programs generated on the Encounter Test platform using Verilog model simulations as the golden standard. Additionally, Source III will convert and generate test programs from the Cadence standard test interface language STIL to a format readable by targeted ATE platforms. Continued in PDF
The 7.6 release of vtran provides significant enhancements to the STIL interfaces, both canned reader module and the STIL output formatter. The ReadBack modules from previous releases have been enhanced to provide cycle-based readback as well as the event-based capabilities. This means that vtran-generated test programs can be directly translated to other tester formats as well as testbench formats for verification. The Agilent (HP) 93000 interface has been enhanced to handle Pincsale capabilities with optimized resource assignments in the dvc files. In addition, numerous new parameters have been added to different interfaces to improve user control and customization of the translated vector data.
The 7.1 release of vtran continues to strengthen the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. This release introduces additional canned reader modules called Read-Back modules which provide a new, efficient way to verify vtran-generated test programs prior to loading them on a tester. These modules can be used by vtran to directly read-back the test programs and then generate a Verilog or VHDL testbench for a re-simulation verification check. Read-Back support for Credence, Agilent (HP93000), Teradyne J750, J973 and Catalyst are included in this release. XMODE support for the Agilent 93000 tester is now available, enabling significant memory size and performance improvements.