Simulate Translate Test

One of the challenges affecting IC test and design is the ability to translate STIL vectors. While many test strategies utilize STIL, WGL or VCD/EVCD formats in the design-to-test flow, they struggle with translations from these vector formats to physical device testers. VTRAN was designed to make it easier to translate STIL to test, converting STIL and other popular formats to over 30 ATE and simulation formats. VTRAN, together with our other products, was created to help make conversions to ATE from STIL, WGL, VCD/EVCD and other formats easy, fast and with maximum flexibility, all within the Vtran User Interface (VUI) environment. Our DFTView product also provides a graphical, timing accurate waveform view of STIL and WGL test programs, allowing you to visualize the actual waveforms being applied to the device under test. Why Source III and VTRAN? VTRAN links Simulation and ATPG to ATE. It is the most affordable,…
EL DORADO HILLS, Calif. and HSINCHU, Taiwan SpringSoft, Inc., a global supplier of specialized IC design software, and Source III, Inc., a leading supplier of test vector translation and analysis tools, announce the availability of Source III’s new DFTView® tool and its integration with SpringSoft’s Verdi™ Automated Debug System. Using both products together, DFT and test Engineers are able to graphically view and debug the contents of industry standard test files in the WGL and STIL formats.   STIL (Standard Test Interface Language – IEEE 1450.1999) and WGL (Waveform Generation Language) are industry standard languages used by Automatic Test Program Generators (ATPG) and Design for Test (DFT) tools to specify test patterns for IC devices.  These languages use complex, high-level language syntax to describe the waveforms which ultimately are applied to an IC device on Automatic Test Equipment (ATE).  It is difficult for DFT and Test engineers to inspect and validate…
SpringSoft, Inc, a global supplier of specialized IC design software, and Source III, Inc, a leading supplier of test vector translation and analysis tools, announce the availability of a new tool, DFTView®, which works in conjunction with SpringSoft's Verdi/nWave products, to give DFT and Test Engineers the ability to graphically view the contents of Industry standard test files in the WGL and STIL formats.

Source III Announces Release 9.2 of VTRAN®

Sunday, 14 November 2010 18:00
Source III announces the release of VTRAN® 9.2 for the Solaris SPARC, Solaris X86 and Linux platforms. This new release continues our commitment to timely and continuous product improvements in response to the ever-changing needs of our customers. Featured in this release are the following:   Enhanced tester interface for the Advantest T2000 tester adding support for per-pin vector formats and handling multiple files with common timing. Improved placement control for general purpose IDDQ insertion mechanism which can insert up to 3 control signals and user-defined IDDQ vectors at IDDQ markers in WGL and STIL files. Improved syntax checkig in WGL reader with more control over special cases. Added ReadBack module for LTX tester interface providing for a validation testbench path on vtran-generated LTX test programs. Added MERGE_TSET process to support character-based waveform timing in STIL and Verigy 93000 formats. Enhanced STIL writer to better support Credence D10 syntax requirements.…

New VTRAN® 9.1 Release

Tuesday, 01 December 2009 09:46
Source III announces the release of VTRAN® 9.1 for the Solaris SPARC, Solaris X86 and Linux platforms. This new release continues our commitment to timely and continuous product improvements in response to the ever-changing needs of our customers. Featured in this release are the following: Enhanced tester interface for the Advantest T2000 tester adding support for scan data on both the T2000 writer and ReadBack module. Enhanced general purpose IDDQ insertion mechanism which can insert up to 3 control signals and user-defined IDDQ vectors at IDDQ markers in WGL and STIL files. Enhanced Verilog testbench output formatters to include vector and cycle count information which corresponds to vectors in the input source file. Very useful when using ReadBack modules for Teradyne, Verigy or Credence to validate test programs. Enhanced TSTL2 writer to better support various combinations of signal grouping and timing. Enhanced MERGE_FILE feature to give more flexibility handling timing…