Simulate Translate Test

We are pleased to announce that, on Monday, Source III released a major update to our VTRAN Software Bundle functionality. After over 2 years of development working directly with Advantest, VTRAN now offers Advantest SmarTest8 Support. This functionality was thanks to the combined efforts of our entire team here at Source III, including Linda, Carrie, Brian, and Frances, and we’re very pleased that our customers can now use our tool to assist them with their Advantest V93000 SmartTest8 testers, and includes: Advantest V93000 SmarTest8 Interface Advantest V93000 SmarTest8 Reader The reader can be used to generate a Verilog or VHDL TestBench file. For those that need assistance in using the VTRAN 10.3 Software Bundle for their Advantest SmarTest support, we have tips and assistance available in our 10.3 Release Notes. Additional Functionality In addition to this major update, we also have added several features that our clients have requested over…
Our support team at Source III is the best in the vector translation business. On occasion, we are asked a great question by our customers, and when we think that the answer may be relevant for other clients, we turn it into a blog post. The following is a recent customer question, followed by the response from our support team: Question: "Does VTRAN allow STIL vector statements with no arguments (signifying no change from the previous vector) or vector statements with vector strings of different lengths when applied to different signal groups?" Answer: The short answer is yes, VTRAN handles this just fine.  It maintains the previous state on any pin not modified in a particular vector.   Longer answer:  Vector statements (shorthand V) in STIL typically only specify changes relative to the previous cycle.  Thus any signal or group not explicitly referenced will retain the previous state, and active…
Question: I have a simulation file in VCD format and want to use VTRAN to generate an ATE device test program.  Because of the complexity of this device, the test program will need to have multiple timesets.  I think I need to use VTRAN's TEMPLATE_CYCLIZATION strategy. How do I get started? Answer: If you have a situation where you need to generate multiple timesets and :        all of timesets have the same cycle length, but you do not have a tester that supports flexible waveform descriptions OR        the timesets have different cycle lengths you do need to use the TEMPLATE_CYCLIZATION strategy.  The feature is quite powerful and described fully in the VTRAN User Guide and in the Applcation Note titled "TEMPLATE CYCLIZATION".   Here are the basics. How does it work? TEMPLATE CYCLIZATION works by applying user created timesets to the original waveform.  VTRAN determines which timeset to apply based on…

Question: How do I choose a Cyclization Strategy?

Thursday, 15 September 2016 10:50
Question: What is cylization and how do I choose a cyclization strategy using the VTRAN Tool Suite? Answer: Event-based formats like VCD and EVCD typically have state data and time entries in the vector file every time there is a state change on any pin. These are considered flat or time-expanded vectors.  Cycle-based formats, used in ATE device test program files, combine all the state transitions that occur in a given time period or cycle into a single vector that references a separate "timing" (i.e. waveform edge times) section of the target format. Cyclization is the process of collapsing the event driven vector data from event-based formats into cycle-based formats . VTRAN has several cyclization flows and the best choice depends on the translation. VCAP STIL_TRANS If the waveforms in the Original Vector File can be represented by cycles of a consistent length, and the target vector format supports flexible…

Question: Masking Sequences with MASK_PINS

Wednesday, 31 August 2016 23:26
At Source III, we do our best to answer each and every question from our clients. Every once in a while we take an excellent question and turn it into a post for anyone using our software. Recently we had a question about the MASK_PINS command, and we're happy to share the answer with you here: Question: I am converting a VCD to an 93K avc vector file and I'm trying to use the MASK_PIN command to change sequences of states on bidirectional pins. Here's a partial VTRAN command file which shows what I'm trying to do: ovf_block   begin     { Define original file format }     script_format VERILOG_VCD;     { Declare pin directions }     inputs BDIR_output_enable;     bidirects B_DATA[3] B_DATA[2] B_DATA[1] B_DATA[0];   end proc_block   begin     { Separate bidirectional data based on a control pin }     BIDIRECT_CONTROL…