Simulate Translate Test

IC (including ASICs) Design-to-test flow is fraught with issues. Although the current methodologies are well established, the programs and test tools are generally inefficient, and in some cases require significant manual inputs and effort in order to move forward in the process. Improving Efficiency, Translations, Analysis and More Every product in Source III’s product line was designed to provide IC design-to-test methodology help to engineers looking for a more streamlined, user friendly, and efficient translation flow. Our products each seek to provide valuable resources to design and test engineers that can be used again and again throughout the chip development process. Two of our four products in particular are worth highlighting: VTRAN – VTRAN is a vector translation program that translates over 30 different popular simulation and ATE vector Formats. VTRAN is used by dozens of the leading names in the electronics and semiconductor industries, translating WGL, STIL, VCD/EVCD to…

Analyze Pin Timing Behavior with VCAP

Monday, 05 October 2015 18:29
One of the challenges facing ASIC test engineers (and all IC test engineers) is analyzing simulation results files from design, especially with regards to pin timing and behavior. Often this analysis has to be completed manually, where the user has to spend hours reviewing simulation data files, determining propagation delays, and extracting input signal behaviors. It can be time consuming, and in some cases impossible depending on the limitations of your software. To address that challenge, Source III created VCAP, a comprehensive simulation data analysis tool with a variety of capabilities to assist IC, and ASIC test engineers with their simulation results analysis. VCAP has many additional features, but today, we wanted to highlight some of the most valuable capabilities as they relate to analysis of pin timing and behavior, which include capabilities such as: Identifying the waveform behavior of input signals Reporting minimum and maximum output delays. Checking for…
Many of our clients use our DFTView product on a Load Sharing Facility (LSF) Platform. To do so does require a few small changes: For this to work correctly your DISPLAY must be properly configured when you connect to your compute server — by passing the -I flag to bsub LSF will typically take care of this for you, for example:   bsub -I DFTView &   You can also try running an Xterm directly on your compute host - this should provide you with an Xterm window where your display settings would again be set for you.  In this case, you could then just run DFTView interactively within that Xterm:   bsub xterm -or- lsrun sh -c "xterm &"   In some situations you may need to use X11 forwarding over ssh when submitting a job - this requires the additional -XF option, and may require you to provide your password and/or…
On occasion you may find that you need to create fake primary ports as a way to get around compression issues in TetraMax. Your WGL File will then contain these fake ports, and when you want to convert the WGL file to test, you'll want these fake ports removed. Thankfully, this process is easy with Source III's VTRAN program. The easiest way to accomplish this is with the DELETE_PINS statement the TVF block - list those fake ports you want to remove during translation e.g.:   DELETE_PINS   test_BIDIR[1],   test_BIDIR[0],   test_clock_a,   test_clock_b,   ...   test_clock_k;   As an alternative approach you could instead use the INPUTS, OUTPUTS and BIDIRECTS statements to list the pins you want to KEEP in your output file.  This is perhaps less convenient here since you need to list every non-fake pin, but it is valuable to be aware of thiis approach.…
One of the challenges affecting IC test and design is the ability to translate STIL vectors. While many test strategies utilize STIL, WGL or VCD/EVCD formats in the design-to-test flow, they struggle with translations from these vector formats to physical device testers. VTRAN was designed to make it easier to translate STIL to test, converting STIL and other popular formats to over 30 ATE and simulation formats. VTRAN, together with our other products, was created to help make conversions to ATE from STIL, WGL, VCD/EVCD and other formats easy, fast and with maximum flexibility, all within the Vtran User Interface (VUI) environment. Our DFTView product also provides a graphical, timing accurate waveform view of STIL and WGL test programs, allowing you to visualize the actual waveforms being applied to the device under test. Why Source III and VTRAN? VTRAN links Simulation and ATPG to ATE. It is the most affordable,…