Simulate Translate Test

Advantest, the largest Automatic Test Equipment vendor in the test engineering market today, nearly always requires translations from common vector formats. VTRAN supports nearly all of the Advantest platforms. Some of the most common uses for our software are to convert between these vector formats to ATE for testing, with dozens of different combinations available. The Most Common Vector Languages VTRAN supports over 30 different vector and ATE formats. 95% of test Advantest translations are: STIL WGL VCD EVCD We do support other vector file formats, but they are rarely paired with Advantest ATE users. Perhaps most importantly, however, we also support nearly all of the Advantest ATE formats. We support: Advantest V93000 (Formerly HP93000 and Agilent 93000) Advantest T2000 Advantest T66XX Advantest T33XX We also have a few additional Advantest ATE releases scheduled for the next coming months. Please stay tuned for updates. Source III VTRAN Translations Advantest is…

Notes on STIL Procedures

Thursday, 12 November 2015 12:32
There are a number of factors that affect to actual waveform that gets assigned to a signal within a Procedure. Procedures in STIL are different than Macros in that all signals revert to undefined (or actually their DefaultState) upon entry to a Procedure whereas signals maintain their last assigned WaveformCharacter (WFC) upon entry to a Macro. This is why it is strongly recommended that all signals be assigned a specific WFC either within or prior to (using Constant or Fixed statements) the first Vector statement in a Procedure. Similarly, upon exit from a Procedure the signal WFC's existing before the Procedure Call are re-instated whereas the WFCs at the end of a Macro carry thru upon exit. For Procedures, here are the things (and rules) which can affect the WFC which ends up on a signal: 1) DefaultState, if it is defined in the Signals block. If not defined it…

Source III's 10.1 Release is Now Live

Thursday, 29 October 2015 00:21
We at Source III are proud to announce that version 10.1 of our software is now live. We've added a variety of feature improvements to all of our software platforms, with enhancements for VTRAN, VCAP, and DFTView that continue to improve upon our industry leading software. Below are some of the changes we've made in version 10.1. What's New in VTRAN 10.1? We have added a new feature for supporting Free Running Clocks in translations from WGL, STIL, and VCD/EVCD to Teradyne J750, Flex+, and iFLEX testers. This support includes Readback modules for these testers when translating back to a Verilog TestBench for Validation. Improved support for LOOP_THRESHOLD and REPEAT_THRESHOLD features to compact test vectors during translations. Further enhancements have been made to our MERGE_FILES capability. Now MERGE_FILES is able to fully support concatenating files with scan data. Support for "escaped" signal names in VTRAN command files to allow for…
In today’s DFT tools, the use of scan insertion to improve test coverage and reduce test pattern volume is very common. All of the major ATPG tool vendors (Synopsys, Cadence and Mentor) offer this approach in their product suites. And indeed this approach has proven to be very effective, together with some other pattern compression techniques, in helping design/test engineers meet the challenges for today’s complex devices. The way in which scan is handled within WGL files is often a source of confusion for engineers using this language as the medium for pattern expression. One primary reason for this confusion is that the scan data expressed in the WGL file is cell data, not shift data. This means that when translating these patterns into an actual test program for ATE a mapping must be done by the translation tool because real device test programs must have shift data. It is…
Today’s logic simulators are some of the most advanced, capable of comprehensive, timing-accurate logic and timing simulations. But many of the languages that utilizes these simulators fail to take advantage of these capabilities. VGEN was created to provide a high level language interface that is fully customizable, able to be tailored to the specific needs of the simulators and testers. The value of this is efficiency. VGEN has been shown to reduce the amount of time spent modifying, creating, and documenting simulation stimulus files by as much as 80%, because it is capable of a variety of functions that are invaluable for those working with CAE/CAD tools, which generally provide sub-adequate solutions for Integrated Circuit and system level designers. VGEN is a feature rich generic stimulus language solution, with features that include: Signal grouping and vectorizing Subroutines with parameter passing Complex logic/arithmetic syntax for algorithmic pattern generation Pattern looping and…