Simulate Translate Test

At Source III, we want to be here to answer your questions. Over the next several months, we will start featuring some of the great questions we've been asked by some of our clients, and answers to help those that may be interested in the same functionality. Question: Can I change the number of columns used when generating AVC (vector) files for the Advantest 93000?  For example, in my input vector file I have the following input pins:   Clocks:  CLK1, CLK2 Signal bus:SIG[3], SIG[2], SIG[1], SIG[0] Data bus: DATA[3], DATA[2], DATA[1], DATA[0]   and I get output vectors which look like this:       R1  tset1  0100110101;   As an example, could I separate the clocks from the busses without resorting to post-processing?   Answer:   VTRAN outputs signals as listed in the original order, unless the INPUTS, OUTPUTS, BIDIRECTS or SIGNAL_ORDER statements are used to define which…
For over 20 years, VTRAN by Source III has been used by DFT engineers to translate between over 30 different ATPG, EDA, simulation, and test vector formats. VTRAN is equipped with many powerful tools, including the ability to support Scan Data structures, a translation feature that is used by some of the leading IC design and test manufacturers around the world. One of the advantages of using VTRAN is that it supports nearly every test, EDA, simulation, and automatic tester equipment used by test engineers today. Most vector translation software, including VTRAN, is capable of translating to and from the following: STIL WGL VCD/EVCD But VTRAN is also capable of reading and writing to dozens of other simulator formats, tester formats, and more, including the following simulator formats: Nanosim LSM HSIM QSIM And the following ASIC Vendor Formats TDL_91 TSTL2 FTDL And the following Tester Formats SVF Chroma Teradyne J750…
Advantest, the largest Automatic Test Equipment vendor in the test engineering market today, nearly always requires translations from common vector formats. VTRAN supports nearly all of the Advantest platforms. Some of the most common uses for our software are to convert between these vector formats to ATE for testing, with dozens of different combinations available. The Most Common Vector Languages VTRAN supports over 30 different vector and ATE formats. 95% of test Advantest translations are: STIL WGL VCD EVCD We do support other vector file formats, but they are rarely paired with Advantest ATE users. Perhaps most importantly, however, we also support nearly all of the Advantest ATE formats. We support: Advantest V93000 (Formerly HP93000 and Agilent 93000) Advantest T2000 Advantest T66XX Advantest T33XX We also have a few additional Advantest ATE releases scheduled for the next coming months. Please stay tuned for updates. Source III VTRAN Translations Advantest is…

Notes on STIL Procedures

Thursday, 12 November 2015 12:32
There are a number of factors that affect to actual waveform that gets assigned to a signal within a Procedure. Procedures in STIL are different than Macros in that all signals revert to undefined (or actually their DefaultState) upon entry to a Procedure whereas signals maintain their last assigned WaveformCharacter (WFC) upon entry to a Macro. This is why it is strongly recommended that all signals be assigned a specific WFC either within or prior to (using Constant or Fixed statements) the first Vector statement in a Procedure. Similarly, upon exit from a Procedure the signal WFC's existing before the Procedure Call are re-instated whereas the WFCs at the end of a Macro carry thru upon exit. For Procedures, here are the things (and rules) which can affect the WFC which ends up on a signal: 1) DefaultState, if it is defined in the Signals block. If not defined it…

Source III's 10.1 Release is Now Live

Thursday, 29 October 2015 00:21
We at Source III are proud to announce that version 10.1 of our software is now live. We've added a variety of feature improvements to all of our software platforms, with enhancements for VTRAN, VCAP, and DFTView that continue to improve upon our industry leading software. Below are some of the changes we've made in version 10.1. What's New in VTRAN 10.1? We have added a new feature for supporting Free Running Clocks in translations from WGL, STIL, and VCD/EVCD to Teradyne J750, Flex+, and iFLEX testers. This support includes Readback modules for these testers when translating back to a Verilog TestBench for Validation. Improved support for LOOP_THRESHOLD and REPEAT_THRESHOLD features to compact test vectors during translations. Further enhancements have been made to our MERGE_FILES capability. Now MERGE_FILES is able to fully support concatenating files with scan data. Support for "escaped" signal names in VTRAN command files to allow for…