Simulate Translate Test

Question: How do I choose a Cyclization Strategy?

Thursday, 15 September 2016 10:50
Question: What is cylization and how do I choose a cyclization strategy using the VTRAN Tool Suite? Answer: Event-based formats like VCD and EVCD typically have state data and time entries in the vector file every time there is a state change on any pin. These are considered flat or time-expanded vectors.  Cycle-based formats, used in ATE device test program files, combine all the state transitions that occur in a given time period or cycle into a single vector that references a separate "timing" (i.e. waveform edge times) section of the target format. Cyclization is the process of collapsing the event driven vector data from event-based formats into cycle-based formats . VTRAN has several cyclization flows and the best choice depends on the translation. VCAP STIL_TRANS If the waveforms in the Original Vector File can be represented by cycles of a consistent length, and the target vector format supports flexible…

Question: Masking Sequences with MASK_PINS

Wednesday, 31 August 2016 23:26
At Source III, we do our best to answer each and every question from our clients. Every once in a while we take an excellent question and turn it into a post for anyone using our software. Recently we had a question about the MASK_PINS command, and we're happy to share the answer with you here: Question: I am converting a VCD to an 93K avc vector file and I'm trying to use the MASK_PIN command to change sequences of states on bidirectional pins. Here's a partial VTRAN command file which shows what I'm trying to do: ovf_block   begin     { Define original file format }     script_format VERILOG_VCD;     { Declare pin directions }     inputs BDIR_output_enable;     bidirects B_DATA[3] B_DATA[2] B_DATA[1] B_DATA[0];   end proc_block   begin     { Separate bidirectional data based on a control pin }     BIDIRECT_CONTROL…
Question: Is there a way for me to control which comments get passed from the OVF file to the TVF file? Answer: Yes.  Using the COMMENTS_FILTER command in the PROC_BLOCK a user can now control which pattern comments get passed from the OVF to the TVF based on time range or content. First, enable comment passing support by using the "COMMENTS ON"  command in the OVF_BLOCK. Next, choose the desired COMMENT_FILTER(s) in the PROC_BLOCK. Examples:      COMMENT_FILTER MATCH_STRING = "FSM7", "comment"; COMMENT_FILTER TIME_RANGE 450, 2850; Use COMMENT_FILTER MATCHING_STRING = "m_string0", "mstring_1", .. to pass only those comments containing at least one of the specified strings.  Up to 10 strings with a length of 2048 characters can be listed. If multiple COMMENT_FILTER MATCH_STRING statements are used, only the last statement is applied. Use COMMENT_FILTER TIME_RANGE t1, t2; to pass only those comments associated with the absolute time range beginning at t1 and…
Question:   While converting a VCD file for the Advantest 93000 'AVC' format, I get thousands of identical repeated vectors. Is there a keyword that will trigger compression of these identical vectors into repeats?     Answer:   When converting from an event-based format like VCD or EVCD (or from a cycle-based format while using the -EXPAND_REPS reader option) VTRAN will explicitly generate a vector for every cycle, even if a vector is identical to the previous one.  Consider this TVF Block section of a VTRAN command file:       TVF_BLOCK       BEGIN         TARGET_FILE = "output.avc";         TESTER_FORMAT HP90000           DVC_FILE = "output.dvc";       END;   It might result in an "output.avc" AVC file which looks in part like this - you can see nine identical vector lines flanked by two different ones:  …
At Source III, we want to be here to answer your questions. Over the next several months, we will start featuring some of the great questions we've been asked by some of our clients, and answers to help those that may be interested in the same functionality. Question: Can I change the number of columns used when generating AVC (vector) files for the Advantest 93000?  For example, in my input vector file I have the following input pins:   Clocks:  CLK1, CLK2 Signal bus:SIG[3], SIG[2], SIG[1], SIG[0] Data bus: DATA[3], DATA[2], DATA[1], DATA[0]   and I get output vectors which look like this:       R1  tset1  0100110101;   As an example, could I separate the clocks from the busses without resorting to post-processing?   Answer:   VTRAN outputs signals as listed in the original order, unless the INPUTS, OUTPUTS, BIDIRECTS or SIGNAL_ORDER statements are used to define which…