News: DFTView and Verdi Give DFT and Test Engineers Visibility into STIL and WGL Files , translate WGL vectors, WGL to ATE, WGL to test, Translate STIL vectors, STIL to ATE, STIL to test,
Simulation to test, ATPG to test, Translate VCD to ATE, VCD to test, Verilog testbench translation, WGL waveform display, STIL waveform display, VCD waveform display, and DFT vector display.

EL DORADO HILLS, Calif. and HSINCHU, Taiwan

SpringSoft, Inc., a global supplier of specialized IC design software, and Source III, Inc., a leading supplier of test vector translation and analysis tools, announce the availability of Source III’s new DFTView™tool and its integration with SpringSoft’s Verdi™ Automated Debug System. Using both products together, DFT and test Engineers are able to graphically view and debug the contents of industry standard test files in the WGL and STIL formats.  

STIL (Standard Test Interface Language – IEEE 1450.1999) and WGL (Waveform Generation Language) are industry standard languages used by Automatic Test Program Generators (ATPG) and Design for Test (DFT) tools to specify test patterns for IC devices.  These languages use complex, high-level language syntax to describe the waveforms which ultimately are applied to an IC device on Automatic Test Equipment (ATE).  It is difficult for DFT and Test engineers to inspect and validate these files before using them on a tester.  DFTView is the industry’s first generic tool that gives engineers the ability to graphically see the actual waveforms defined by these intermediate test languages.

“The integration between our Verdi solution and Source III’s DFTView is a natural progression for us.  Engineering teams can now take advantage of the visualization power of Verdi to understand the intended behavior of test files,” said Thomas Li, director of product marketing at SpringSoft.

In addition to graphically displaying the STIL or WGL files, DFTView checks the syntax of these files and generates error messages when the files contain errors.  This is particularly helpful if the files have been hand-edited or contain manually generated sections.  A correspondence between the vector lines in the WGL or STIL source file and waveform positions in the waveform display are maintained by the tool, which allows the user to view specific corresponding locations in each file.

“Source III has worked closely with key customers such as Qualcomm to provide features in DFTView that are most useful to engineers dealing with moving test vectors to ATE, and we will continue to do so with future enhancements to our products”, said John Cosley, CEO of Source III.  “DFTView together with VTRAN, our vector translation product, gives our customers a powerful set of tools for handling their EDA-to-Test flow”.

About DFTView and Verdi

The industry’s first STIL and WGL viewer, DFTView offers a visual (waveform) view of WGL and STIL files, maintaining a correspondence between vector lines in the source file and equivalent locations in the waveform trace.   It uses the same WGL and STIL reader technology that is used by VTRAN™, Source III’s industry-leading vector translation program.  The product also allows users to edit the source files and see the immediate effects on the waveforms.  It is available on Linux and Solaris platforms, both 32 and 64-bit versions.  Users must have a SpringSoft Verdi/nWave software license to run DFTView.  The product is available immediately from Source III as an option for Verdi users.  Contact Source III at (916) 941-9403 or corp@sourceiii.com for additional technical information, evaluation copies and pricing.

The Verdi Automated Debug System is SpringSoft’s flagship product for advanced debug. It cuts debug time in half by automating the process of comprehending how complex IC and SoC designs work, particularly unfamiliar legacy design elements or third-party intellectual property. The full-featured system automates behavior tracing over time with its unique analysis engines, provides a powerful set of design views to visualize and help analyze cause-and-effect relationships, and uses patented techniques to reveal the functional operation and interaction between the design, assertions and system testbench.

About SpringSoft

SpringSoft, Inc. (TAIEX: 2473) is a global supplier of specialized automation technologies that accelerate engineers during the design, verification and debug of complex digital, analog and mixed-signal ICs, ASICs, microprocessors, and SoCs. Its award-winning product portfolio features the Novas™ Verification Enhancement and Laker™ Custom IC Design solutions used by more than 400 of today's leading IDM and fabless semiconductor companies, foundries, and electronic systems OEMs. Headquartered in Hsinchu, Taiwan, SpringSoft is the largest company in Asia specializing in IC design software and a recognized industry leader in customer service with more than 400 employees located in multiple R&D sites and local support offices around the world. For more information, visit www.springsoft.com.

About Source III

Headquartered in El Dorado Hills, California, Source III is a privately held company founded in 1983 that develops and licenses software tools linking EDA to Test.  Its vector translator, VTRAN, converts logic simulation data file and ATPG-generated files s to more than 30 popular ATE and EDA formats and is an industry standard.  For the latest news and information on Source III, visit www.sourceiii.com.

Verdi, Novas and Laker are trademarks of SpringSoft, Inc.  DFTView and VTRAN are trademarks of Source III, Inc. All other trademarks or registered trademarks are the property of their respective owners.

SpringSoft, Inc, a global supplier of specialized IC design software, and Source III, Inc, a leading supplier of test vector translation and analysis tools, announce the availability of a new tool, DFTView™, which works in conjunction with SpringSoft's Verdi/nWave products, to give DFT and Test Engineers the ability to graphically view the contents of Industry standard test files in the WGL and STIL formats.

Source III announces the release of VTRAN 9.2 for the Solaris SPARC, Solaris X86 and Linux platforms.

This new release continues our commitment to timely and continuous product improvements in response to the ever-changing needs of our customers. Featured in this release are the following:

• Enhanced tester interface for the Advantest T2000 tester adding support for per-pin vector formats and handling multiple files with common timing.
• Improved placement control for general purpose IDDQ insertion mechanism which can insert up to 3 control signals and user-defined IDDQ vectors at IDDQ markers in WGL and STIL files.
• Improved syntax checkig in WGL reader with more control over special cases.
• Added ReadBack module for LTX tester interface providing for a validation testbench path on vtran-generated LTX test programs.
• Added MERGE_TSET process to support character-based waveform timing in STIL and Verigy 93000 formats.
• Enhanced STIL writer to better support Credence D10 syntax requirements.
• Enhanced ADD_PIN support for adding user-defined bidirectional signals to file.

In addition to these highlights, VTRAN has had on-going improvements to its speed, memory efficiency and overall program quality. VTRAN has played an important roll in linking simulation/ATPG to test for over 18 years with thousands of successful vector translations.

Source III announces the release of VTRAN 9.1 for the Solaris SPARC, Solaris X86 and Linux platforms.

This new release continues our commitment to timely and continuous product improvements in response to the ever-changing needs of our customers. Featured in this release are the following:

• Enhanced tester interface for the Advantest T2000 tester adding support for scan data on both the T2000 writer and ReadBack module.
• Enhanced general purpose IDDQ insertion mechanism which can insert up to 3 control signals and user-defined IDDQ vectors at IDDQ markers in WGL and STIL files.
• Enhanced Verilog testbench output formatters to include vector and cycle count information which corresponds to vectors in the input source file. Very useful when using ReadBack modules for Teradyne, Verigy or Credence to validate test programs.
• Enhanced TSTL2 writer to better support various combinations of signal grouping and timing.
• Enhanced MERGE_FILE feature to give more flexibility handling timing of non-common signals for concatenated files.
• Added ability to pass STIL statement labels as comments to ATE writers.
• Updated FSDB (Springsoft) writer.
• VTRAN now supports Include files in the command file facilitating the use of common files.

In addition to these highlights, VTRAN has had on-going improvements to its speed, memory efficiency and overall program quality. VTRAN has played an important roll in linking simulation/ATPG to test for over 18 years with thousands of successful vector translations.

Source III and the China Electronics Standardization Institute (CESI) announce an agreement whereby CESI will provide sales and technical support for all of Source III's products in mainland China.

CESI provides comprehensive services and support of electronic information technology and is under the MII (Ministry of Information Industry). It is located in Beijing with two offices there:

• Sales contact Main Office: Zhong Weijun
• No. 1 An Ding Men Dong Da Jie
• Beijing, P.R. China, 100007
• Tel: +86-010-84029279
• Fax: +86-010-84029104

• Sales contact Yizhuang Industrial Park Office: Zhong Mingchen
• Tel: +86-010-67831826
• Fax: +86-010-67831823
• E-mail: ict@cesi.ac.cn

Personnel from the Electronic Measurement and Calibration Center of CESI have very broad expertise in design and test. This expertise will be very valuable in supporting Source III's products there.

Brugge, Belgium / El Dorado Hills, CA, USA

Q-Star Test nv., the premier supplier of advanced high speed and high accurate IDD test and measurement solutions, and Source III, Inc., a leading developer of test conversion and verification programs, announce a strategic partnership and collaboration to enable reducing test engineering efforts, improved test validation and faster test conversion for enhanced chip quality.

Q-Star Test offers IDDX and ISSX monitor solutions, supporting true IDDQ, delta IDDQ, IDDT and analog IDD and the complementary ISSx test strategies applicable to digital, analog, and mixed signal circuits. Q-Star Test's measurement hardware is ATE independent and outperforms other available ATE related IDD test hardware by at least a factor of 100 (with respect to measurement speed and accuracy). The hardware solutions are complemented with application and test strategy related consulting and training services.

Source III Simulation and Test Data Management tools provide for quick and easy creation of simulation vector data (VGEN), translation between over 30 popular simulator/ATPG formats and numerous tester formats (VTRAN), and verification/analysis of simulation data files (VCAP). All Source III products are supported on Sun Solaris, HPUX, and Linux (32 and 64-bit) platforms.

The partnership and collaboration targets the automated insertion of Q-Star Test IXXX module control using Source III's VTRAN tool into the test pattern data either when generating a test program starting from ATPG data or when translating from one ATE format to another.

Q-Star Test and Source III are happy to announce that as a first result of the cooperation a push-button automated WGL based VTRAN flow has been established and validated by customers that allows automated insertion of Q-Star Test module control into the test pattern data, resulting in a ready to use test program. Further work is focusing on setting up a similar STIL based flow which will be available within 30 days.

"The realization of the automated WGL based VTRAN module control insertion flow drastically reduces test engineering efforts when using Q-Star Test products and brings a high-level, easy to use push-button solution, eliminating human errors and related test pattern debugging efforts." said Dr. Hans Manhaeve, Q Star Test's President and CEO. "In addition, such an approach is platform independent and paves the way to ensuring high quality testing at minimal cost."

"We see this partnership as a tremendous opportunity to help the semiconductor industry find effective ways to control test costs. Adding this functionality to our VTRAN tool helps our customers to shorten engineering time and easily endorse advanced IDDX and Issx test methodologies" said John Cosley, Source III's President & CEO. "From this perspective, the cooperation between Source III and Q-Star Test provides solutions that overcome issues and challenges surrounding advanced semiconductor test."

The partnership between Q-Star Test and Source III will allow customers to benefit from the combination of products and services offered. By combining Source III's software solutions with Q-Star Test's measurement hardware, an easy route toward the implementation of a (supply) current based test strategy applicable in a production test environment is created. Meanwhile, customers will benefit from a reduction of test engineering efforts, test program debug time, test time and costs, and an improvement of product quality. The partnership will also allow Q-Star Test and Source III to reinforce their market position and to provide the semiconductor market with cost effective and powerful soft- and hardware solutions to reduce test time and costs.

About Q-Star Test nv

Q-Star Test is the premier provider of current-based (IDD/ISS) test and measurement solutions. The company offers IDDx and ISSx measurement solutions, supporting true IDDQ, ISSQ, delta IDDQ/ ISSQ, IDDT, and analog IDD test strategies, which apply to digital, analog, and mixed-signal circuits. The company provides standard and customized products and services. Q-Star Test owns several supply current measurement technologies covered by a set of strategic patents. These technologies allow the creation of high-speed, high-accuracy supply current monitors, with the unique characteristic of being virtually transparent to the device under test and the automatic test equipment (ATE). Q-Star Test's worldwide web address is http://www.qstar.be. The company is located at L. Bauwensstraat 20, B-8200 Brugge, Belgium.

About Source III

Source III was founded in 1980 to provide full custom and semicustom design services, making extensive use of gate array and standard cell design methodologies. During the first 6 years of its existence dozens of custom and semicustom design projects were completed for many large electronics companies.

Source III provides vector file translation services involving the translation of logic simulation data files and ATPG-generated files to vector formats either for physical device testers or for other logic simulators and analysis tools. We support translations between more than 30 formats.

The current focus of the company is providing CAE tools which aid the designer in the dataintensive aspects of design/simulation/test. This includes stimulus generation (VGEN), simulation/ATPG data translation (VTRAN and test option), and simulation data verification/analysis (VCAP). All areas in which growing needs are not being met by the major CAE vendors. Source III' worldwide web address is www.sourceiii.com The company is located at 3941 Park Drive, #20-342, El Dorado Hills, CA 95762.

Contacts

• Q-Star Test
• Hans Manhaeve
• Tel: +32 50 315744
• Fax: +32 40 312350
• Hans.Manhaeve@qstar.be

• Source III
• John Cosley
• Tel: 916-941-9403
• FAX: 916-941-9404
• John@sourceiii.com

Acronyms and Definitions

ATE	Automatic Test Equipment
ATPG	Automatic Test Pattern Generation
DFT	Design-for-Test
EDA	Electronic Design Automation
IDD	Device supply current
IDDQ	Quiescent supply current
ISS	Device ground current
ISSQ	Quiescent ground current
IDDT	Transient supply current - switching current
WGL	Waveform Generation Language
STIL	Standard Test Interface Language (IEEE Std.1450-1999)

Magma Design Automation, a provider of chip design software, announced that it has partnered with Source III to offer a direct path from Talus ATPG and Talus ATPG-X to a variety of testers via Source III's VTRAN. With a foundation in IEEE 1450 STIL and through its collaboration with Source III, Magma is working to improve test quality, streamline test flow and reduce test costs. Continued in PDF

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, and Source III, Inc., a leading developer of test conversion and verification programs, have announced a collaboration to enable improved test validation and faster test conversion for enhanced chip quality.

The joint effort expands the silicon design chain to include validation by Source III of test programs developed on the Cadence® Encounter® Test automated test program generation (ATPG) platform, as well as conversion of semiconductor test programs to targeted automatic-test-equipment (ATE) platforms.

Source III will validate test programs generated on the Encounter Test platform using Verilog model simulations as the golden standard. Additionally, Source III will convert and generate test programs from the Cadence standard test interface language STIL to a format readable by targeted ATE platforms. Continued in PDF

The 7.6 release of vtran provides significant enhancements to the STIL interfaces, both canned reader module and the STIL output formatter. The ReadBack modules from previous releases have been enhanced to provide cycle-based readback as well as the event-based capabilities. This means that vtran-generated test programs can be directly translated to other tester formats as well as testbench formats for verification. The Agilent (HP) 93000 interface has been enhanced to handle Pincsale capabilities with optimized resource assignments in the dvc files. In addition, numerous new parameters have been added to different interfaces to improve user control and customization of the translated vector data.

The 7.1 release of vtran continues to strengthen the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. This release introduces additional canned reader modules called Read-Back modules which provide a new, efficient way to verify vtran-generated test programs prior to loading them on a tester. These modules can be used by vtran to directly read-back the test programs and then generate a Verilog or VHDL testbench for a re-simulation verification check. Read-Back support for Credence, Agilent (HP93000), Teradyne J750, J973 and Catalyst are included in this release. XMODE support for the Agilent 93000 tester is now available, enabling significant memory size and performance improvements.

The 7.0 release of vtran strengthens the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. This release introduces a new set of canned reader modules called Read-Back modules which provide a new, efficient way to verify vtran-generated test programs prior to loading them on a tester. These modules can be used by vtran to directly read-back the test programs and then generate a Verilog or VHDL testbench for a re-simulation verification check. Read-Back support for Credence, Agilent (HP93000), Teradyne J750 and Catalyst are included in this release. The STIL reader has also undergone substantial upgrades in this release, adding support for many of the popular 1450.1 features needed to handle today's complex SOC designs.

The 6.5 release of vtran introduces the TEMPLATE_CYCLIZATION feature which provides support for the cyclization of print-on-change simulation data to cycle-based data for testers, where multiple timesets are embedded in the data. Thus, popular VCD files with dynamically changing timing can now be translated to test programs using this feature. Also in this release is initial support for the ITS900 tester. Other new features include enhanced signal masking capabilities, dramatically improved WGL reader performance, a new PIN_INFO_FILE feature, and numerous interface enhancements and upgrades.

The new 6.0 release of vtran enhances a number of interfaces including the following; STIL reader adds support for many .1 (dot 1) extensions, MUX support for WGL, passing of structural loops and repeats between formats, enhanced Verilog and VHDL testbench features plus many more. An initial IMS MEM output format is included in this release. Also this release includes the first 64-bit Solaris version of vtran, pushing its ability to handle very large files beyond the 2GB limit.. With this release, Source III continues its constant improvements and feature enhancements of vtran, based upon customer needs and requests.

This new release of VTRAN adds support for the Teradyne J971 and J973 testers, in addition to significant enhancements to signal masking processing and the direct reading of gzip'ed files. A new interface to the HSIM simulator from Nassda is also included in this release. The Verilog and VHDL testbench interfaces were both enhanced with additional optional parameters to further customize testbenches.

Source III joins Synopsys' In-Sync Program to provide a joint solution for quick and easy translation of TetraMAX-generated vectors in either WGL or STIL format to test programs for Credence, Teradyne and HP testers. Using vtran, users can readily translate large scan-based vector sets generated by ATPG products into ready-to-use test programs. Click here for more details.

With the release of VTAN 4.6, Source III announces support for the HP83000 and HP93000 testers as target formats for vector translations from WGL, STIL, Verilog VCD and many other formats. With this new interface, the popular HP testers become easily accessible to users with almost any simulation or ATPG-generated vector sets.

Source III announces the release of VTRAN 4.6 with several enhancements to vector translations and support for several new tester formats. With this release, VTRAN now fully supports translations of vector data which include scan chains and scan-formatted data from the popular WGL, as well as the new IEEE STIL, vector formats to the Teradyne (Catalyst and J750), Credence, HP83000/93000 and HP-3070 (PCF) tester formats, as well as numerous ASIC (TSTL2, TDL_91, ..) and simulator formats (Verilog/VHDL testbench, ..). One of the primary focuses of this new release was the enhanced support of scan data during translation between popular simulator and tester formats. This is an increasingly more common need as scan-based DFT and ATPG tools, such as Synopsys' Design Compiler and new TetraMAX(tm), create vector sets for large complex designs. Support for additional tester formats are planned for release over the next year.

The latest 4.6 Release of VTRAN now includes support for reading the new IEEE Standard Test Interface Language (1450) vector files. With this improved canned reader, VTRAN can handle translations from STIL to a variety of testers (including Teradyne, Credence, HP83000/93000 and HP-3070 PCF), ASIC formats such as TSTL2 and TDL_91, and simulator formats such as Verilog and VHDL testbenches. As tools that generate vector data begin to standardize on this new IEEE standard format, the need for a bridge to the numerous other formats accepted by today's simulation tools and testers increases. In addition to providing this bridge, VTRAN also can be effectively used for verifying tools that generate STIL by providing a path back to simulation - essentially closing the loop. A STIL writer is also under development for release next year.