Simulate Translate Test

Our team at Source III tries to stay up to date with the latest in integrated circuit design and research. The other day, we came across this interesting article at TechXplore, talking about the research currently conducted at UC Riverside. Researchers have been able to speed up the reliability testing process considerably, and can now use electromigration to determine how quickly these circuits fail and how well they withstand the tests of time. We encourage you to read the article for yourself by following this link:https://techxplore.com/news/2018-06-electromigration-temperatures-circuits-hours-year.html
There is perhaps no more complex integrated circuit than the human brain. So it stands to reason that someday an IC may benefit from mimicking the connections in the brain. The other day, researcher Cindy Yang Yi won an award for her research into developing these types of circuits. Yi won the National Science Foundation's Faculty Early Career Development Award for her work creating the architecture for this type of circuit to mimic neurons using neuromorphic computing systems. Read more about Yi, these unique integrated circuit designs, and her award at the Augusta Free Press.  
Here at Source III, we make every effort to continue with updates that save time, improve efficiency, and help you create better products for your customers. We’re proud to announce that version 10.5.2 of the VTRAN product bundle is now live. The following are some of the main enhancements, organized by product. VTRAN Verilog testbenches (READMEM, FILE_IO, and PALLADIUM) now store comment to new datafile and the testbench will display comments right before/after a mismatch, or with the optional -ALL_COMMENTS param in the SIMULATOR command, will display *all* comments. Introducing new PREPROCESS and POSTPROCESS commands which accept external programs or pipelines to operate on the OVF file immediately before VTRAN processing, and the TVF file after translation is complete. Multiple enhancements to the SmarTest8 readback module, supporting translations from ST8 to cycle-based targets such as STIL, WGL, 93K, Teradyne etc. Additional warnings to cover situations where unexpected output may result.…
The answer is robots. Source III’s vector translation software works with both the Teradyne FLEX (iFLEX, microFLEX, and ultraFLEX), J750 (and J750+), and Catalyst formats. Every once in a while, we like to check in on recent Teradyne news to see what else is new in this ATE company’s plans. Last month, we found out that Teradyne has recently acquired a company called MiR. What does MiR do? They create what’s known as Mobile Industrial Robots. Here’s one of these robots in action: Teradyne has a financial focus in automation, which includes not only its automatic test equipment, but also the automation in the industrial and logistics industries. Thus, the acquisition of MiR is likely the company’s way of furthering that vision, investing in a company that offers a unique automation tool for industries that benefit from greater efficiency and reliability. It also furthers their goal of investing in automated…
At Source III, our support team makes every effort to assist you with our VTRAN, DFTView, VCAP, and VGEN software. Sometimes we receive questions that we believe are important for sharing with a wider audience. Recently, we received the following question that we thought would interest other clients that use our products. If you happen to have any questions about VTRAN, or any of our products, feel free and contact our support team at any time. Q: Is it possible to rename a scalar signal to a one-bit bus in VTRAN? For example, if I have a signal named Bus A in my original vector file, and I would like it to be written to the target file as BUS A[0], is that possible? What if I want to go the other direction from single bit-bus to scalar? A: Yes. While you should use the original pin name BUS_A in the OVF…