WGL to ATE, VCD to test, translate WGL vectors,WGL to test, Translate STIL vectors, STIL to ATE, STIL to test,
Simulation to test, ATPG to test, Translate VCD to ATE, VCD to test, WGL waveform display, STIL waveform display, VCD waveform display, and DFT vector display.

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Customer Quotes

"VTRAN is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with SourceIII has been positive and their support is extremely responsive and timely."

Khris Kofford

ON Semiconductor
Customer Quotes

"We currently use Vtran for translating wgl, evcd and vcd vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases."

Stuart Go

Staff Engineer
Open-Silicon, Inc.
Customer Quotes

"We use VTRAN to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly."

Wolfgang Schoell

Product/Test Engineer
Texas Instruments
Customer Quotes

"Source III VTRAN tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion."

Padma Penmatsa

Product Development Engineer
Marvell Semiconductors, Folsom
The Source III Promise

The success of our products is measured by your success with them. Source III will partner with you to make sure that our products are effective in meeting your needs.

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About Source III

Source III's Simulation and Test Data Management tools focus on the creation, translation and analysis for vector data used or generated by logic simulators, ATPG and ATE. Our premier product, VTRAN, links simulation/ATPG vector data to ATE and other CAE tools. VGEN provides a high-level language for quick and easy creation of simulation vector data, and VCAP performs verification/analysis of simulation data files. All Source III products are supported on Sun Solaris SPARC, Solaris X86 and Linux platforms (32 and 64-bit).

  • VTRAN - a program which reads the state/time information from simulation or ATPG-generated data files, performs some optional processing on this data and then re-formats it for any of over 30 popular logic simulators and ATE. A powerful link between CAE and Test.
  • VCAP - comprehensive simulation data comparison and analysis program.
  • VGEN - a stimulus generation language which reduces the time required to create, modify, document, and maintain simulation stimulus files by up to 80%.
  • DFTView - a powerful interface tool which connects high-level test languages WGL and STIL to popular graphical waveform display tools, enabling users to see, edit and validate the actual waveforms described in the test languages.