Simulate Translate Test

About Source III

Source III's Simulation and Test Data Management tools focus on the creation, translation and analysis for vector data used or generated by logic simulators, ATPG and ATE. Our premier product, VTRAN®, links simulation/ATPG vector data to ATE and other CAE tools. VGEN® provides a high-level language for quick and easy creation of simulation vector data, and VCAP® performs verification/analysis of simulation data files. For developers/OEMs, we also recently released DFTDirect®, which provides direct access to vector data, flow information, and structural information for WGL and STIL files. All Source III products are supported on Sun Solaris SPARC, Solaris X86 and Linux platforms (32 and 64-bit).

Source III was founded in 1980 to provide full custom and semicustom design services, making extensive use of gate array and standard cell design methodologies. During the first 6 years of its existence dozens of custom and semicustom design projects were completed for many large electronics companies. From here it evolved into a leading provider of CAE-to-Test software tools. It's vector file translation software (VTRAN®) links logic simulation data files to vector formats either for physical device testers (ATE) or for other logic simulators and analysis tools. We support translations between more than 30 formats including:

From: To:
WGL Teradyne testers
STIL Credence testers
Verilog VCD & EVCD Verigy/Agilent 83000/93000
LSIM HP 3070 testers
Mentor Log IMS testers
QSIM ITS9000 testers
plus many more Advantest testers
  Verilog/VHDL Testbench
  plus many more

Product Support

Customer Quotes

  • We currently use VTRAN for translating WGL, EVCD and VCD vectors to be used on various Verigy and Teradyne platforms. Their feature set has allowed us to perform vector manipulation instead of writing Perl scripts. Their support has been very responsive and they are open to additional features on future releases.
  • Source III VTRAN® tool has been very efficient to translate VCD, WGL, and STIL vectors to Teradyne UFLEX and Verigy 93000 ATE formats. Their response to add or implement new features as per customer needs is impeccable and steadfast. I would highly recommend using this tool to any test engineer for vector conversion
  • Intrinsix Uses VTRAN® to Speed Vector Translation Flow "I had one customer who used VHDL for RTL, Verilog for gate level simulation, and sometimes used EPIC tools. Getting vectors into the various formats was a nightmare. VTRAN® made the translation process easy and seamless. Plus, WGL or STIL for the test group. Support from Source III has also been quite impressive. In one case, they wrote a bug fix for me in under a day." John Weiland Intrinsix Consultant  
  • Sanera Utilizes Full Featured VTRAN® to Convert Functional and ATPG Vectors "We chose VTRAN® because it can handle multiple simulation file formats (including VCD and WGL) from a single tool. VTRAN's commands are easy to use. The flexibility in pin mapping, masking outputs, and generating scan-based vectors proves to be tremendously helpful. And most of all, Source III provides excellent, fast response to our support needs. This helps us to get things moving very quickly - making good solid progress." Ken ChenTest Engineering Manager
  • We use VTRAN® to translate WGL or TDL vectors to Teradyne J750 and Flex format. The produced patterns work fine and adaptation to a new device pinout can be done easy and quickly.
  • VTRAN® is currently our tool of choice for converting MS digital test patterns between various logic simulation formats and WGL/STIL. Our experience with Source III has been positive and their support is extremely responsive and timely.
  • 1
  • 2
  • 3
  • 4
  • 5
  • 6